WM8281ECSSLASHR datasheet(235/392 Pages) CIRRUS

235 / 392 page

WM8281

Rev 4.0

235

DIGITAL AUDIO INTERFACE FUNCTION (AIFnTXLRCLK)

GPn_FN = 00h.

The WM8281 provides three digital audio interfaces (AIF1, AIF2 and AIF3).

Under default conditions, the input (RX) and output (TX) paths of each interface use the respective

AIFnRXLRCLK signal as the frame synchronisation clock. If desired, the output (TX) interface can be

configured to use a separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC registers

as described in “Digital Audio Interface Control”.

The AIFnTXLRCLK function is selected on the respective GPIO pin by setting the GPIO registers as

described in “GPIO Control”.

BUTTON DETECT (GPIO INPUT)

GPn_FN = 01h.

Button detect functionality can be selected on a GPIO pin by setting the respective GPIO registers as

described in “GPIO Control”. The same functionality can be used to support a Jack Detect input

function.

It is recommended to enable the GPIO input de-bounce feature when using GPIOs as button input or

Jack Detect input.

The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable

de-bounce controls. Note that GPn_LVL is not affected by the GPn_POL bit.

The de-bounced GPIO signals are also inputs to the Interrupt control circuit. An interrupt event is

triggered on the rising and falling edges of the GPIO input. The associated interrupt bits are latched

once set; it can be polled at any time or used to control the IRQ signal.

See “Interrupts” for more

details of the Interrupt event handling.

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)

GPn_FN = 01h.

The WM8281 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting

the “GPIO Output” function as described in “GPIO Control”.

The output logic level is selected using the respective GPn_LVL bit. Note that the GPn_LVL registers

are ‘write only’ when the respective GPIO pin is configured as an output.

The polarity of the GPIO output can be inverted using the GPn_POL registers. If GPn_POL=1, then

the external output will be the opposite logic level to GPn_LVL.

INTERRUPT (IRQ) STATUS OUTPUT

GPn_FN = 02h, 03h.

The WM8281 has an Interrupt Controller which can be used to indicate when any selected Interrupt

events occur. An interrupt can be generated by any of the events described throughout the GPIO

function definition above. Individual interrupts may be masked in order to configure the Interrupt as

required. See “Interrupts” for further details.

The Interrupt Controller supports two separate Interrupt Request (IRQ) outputs. The IRQ1 or IRQ2

status may be output directly on a GPIO pin by setting the respective GPIO registers as described in

“GPIO Control”.

Note that the IRQ1 status is output on the IRQ

¯¯¯ pin at all times.

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