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WM8281ECS/R Scheda tecnica(PDF) 239 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 239 Page - Cirrus Logic

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WM8281
Rev 4.0
239
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT
GPn_FN = 08h, 09h.
The WM8281 incorporates two Pulse Width Modulation (PWM) signal generators which can be
enabled as GPIO outputs. The duty cycle of each PWM signal can be modulated by an audio source,
or can be set to a fixed value using a control register setting.
The Pulse Width Modulation (PWM) outputs may be output directly on a GPIO pin by setting the
respective GPIO registers as described in “GPIO Control”.
See “Digital Core” for details of how to configure the PWM signal generators.
Note that the PWM output should always be disabled (PWMn_ENA=0, as described in Table 22)
whenever the system clock, SYSCLK, is disabled. Failure to do this may result in a persistent logic ‘1’
DC output from the PWM generator. See “Clocking and Sample Rates” for details of system clocking
and the associated control requirements.
HEADPHONE DETECTION STATUS OUTPUT
GPn_FN = 12h.
The WM8281 provides a headphone detection circuit on the HPDETL and HPDETR pins to measure
the impedance of an external load connected to the headphone outputs.
See “External Accessory
Detection
” for further details.
A logic signal from the headphone detection circuit may be output directly on a GPIO pin by setting
the respective GPIO registers as described in “GPIO Control”. This logic signal is set low when a
Headphone Detect measurement is triggered, and is set high when the Headphone Detect function
has completed. A rising edge indicates completion of a Headphone Detect measurement.
The headphone detection circuit is also an input to the Interrupt control circuit. An interrupt event is
triggered whenever a headphone detection measurement has completed. Note that the HPDET_EINT
flag is also asserted when the headphone detection is initiated. The associated interrupt bit is latched
once set; it can be polled at any time or u
sed to control the IRQ signal. See “Interrupts” for more
details of the Interrupt event handling.
MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT
GPn_FN = 13h.
The WM8281 provides an impedance measurement circuit on the MICDETn pins to detect the
connection of a microphone or other external accessory.
See “External Accessory Detection” for
further details.
A logic signal from the microphone detect circuit may be output directly on a GPIO pin by setting the
respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a pulse
duration of 31
s whenever an accessory insertion, removal or impedance change is detected.
The microphone detection circuit is also an input to the Interrupt control circuit. An interrupt event is
triggered whenever an accessory insertion, removal or impedance change is detected. The
associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ
signal. See “Interrupts” for more details of the Interrupt event handling.
HEADPHONE ENABLE STATUS OUTPUT
GPn_FN = 2Fh, 30h, 31h, 32h, 33h, 34h.
Whenever a headphone output path is enabled or disabled, a pop-suppression control sequence is
triggered. Status outputs indicating the progress of these sequences are provided. Note that this
provides
See “Output Signal Path” for details of the Output Enable functions.
A logic signal from the Headphone Enable control functions may be output directly on a GPIO pin by
setting the respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a
short pulse duration (approx. 100ns) whenever the respective control sequence has completed. The
headphone control sequence status outputs are described in Table 92.
The Headphone Enable control sequences also provide inputs to the Interrupt control circuit. An
interrupt event is triggered on completion of the respective control sequence. The associated interrupt
bits are latched once set; they can be polled at any time or used to control the IRQ signal. See
“Interrupts” for more details of the Interrupt event handling.



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