WM8281ECSSLASHR datasheet(238/392 Pages) CIRRUS

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WM8281

238

Rev 4.0

FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT

GPn_FN = 0Ch, 0Dh, 0Fh, 10h.

The WM8281 supports FLL status flags, which may be

used to control other events. See “Clocking

and Sample Rates

” for more details of the FLL.

The ‘FLL Clock OK’ signals indicate that the respective FLL has started up and is providing an output

clock. The ‘FLL Lock’ signals indicate whether FLL Lock has been achieved.

The FLL Clock OK and FLL Lock signals may be output directly on a GPIO pin by setting the

respective GPI

O registers as described in “GPIO Control”.

The FLL Clock OK and FLL Lock signals are inputs to the Interrupt Controller circuit. An interrupt

event is triggered on the rising and falling edges of these signals. The associated interrupt bits are

latched once set; they

can be polled at any time or used to control the IRQ signal. See “Interrupts” for

more details of the Interrupt event handling.

FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT

GPn_FN = 05h, 06h.

Clock outputs derived from the FLLs may be output on a GPIO pin. The GPIO output from each FLLn

(where ‘n’ is 1 or 2) is controlled by the respective FLLn_GPCLK_DIV and FLLn_GPCLK_ENA

registers, as described in Table 91.

It is recommended to disable the clock output (FLLn_GPCLK_ENA=0) before making any change to

the respective FLLn_GPCLK_DIV register.

Note that the FLLn_GPCLK_DIV and FLLn_GPCLK_ENA registers affect the GPIO outputs only; they

do not affect the FLL frequency. The maximum output frequency supported for GPIO output is noted

in the “Electrical Characteristics”.

The Frequency Locked Loop (FLL) Clock outputs may be output directly on a GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”.

See “Clocking and Sample Rates” for more details of the WM8281 system clocking and for details of

how to configure the FLLs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R394

(018Ah)

FLL1 GPIO

Clock

7:1

FLL1_GPCLK_DI

V [6:0]

06h

FLL1 GPIO Clock Divider

00h to 06h= Divide by 6

07h = Divide by 7

08h = Divide by 8

09h = Divide by 9

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL1_GPCLK_DIV)

FLL1_GPCLK_EN

FLL1 GPIO Clock Enable

0 = Disabled

1 = Enabled

R426

(01AAh)

FLL2 GPIO

Clock

7:1

FLL2_GPCLK_DI

V [6:0]

06h

FLL2 GPIO Clock Divider

00h to 06h= Divide by 6

07h = Divide by 7

08h = Divide by 8

09h = Divide by 9

…

7Fh = Divide by 127

(FGPIO = FVCO / FLL2_GPCLK_DIV)

FLL2_GPCLK_EN

FLL2 GPIO Clock Enable

0 = Disabled

1 = Enabled

Table 91 FLL Clock Output Control

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