WM8281ECSSLASHR datasheet(122/392 Pages) CIRRUS

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WM8281

122

Rev 4.0

DSP FIRMWARE CONTROL

The WM8281 digital core incorporates four DSP processing blocks, capable of running a wide range

of audio enhancement functions. Different firmware configurations can be loaded onto each DSP,

enabling the WM8281 to be highly customised for specific application requirements. Synchronisation

of different DSPs is supported, and shared data memory space is provided for the DSP2 and DSP3

blocks; these features enable enhanced processing capabilities for the associated DSPs.

Examples of the DSP functions include Virtual Surround Sound (VSS), Multiband Compressor (MBC),

and signal enhancements such as Ez2 Hear™. Note that it is possible to implement more than one

type of audio enhancement function on a single DSP; the precise combination(s) of functions will vary

from one firmware configuration to another.

DSP firmware can be configured using Cirrus Logic-supplied software packages. A software

programming guide can also be provided to assist users in developing their own software algorithms -

please contact your local Cirrus Logic representative for further information.

In order to use the DSP blocks, the required firmware configuration must first be loaded onto the

device by writing the appropriate files to the WM8281 register map. The firmware configuration will

comprise Program, Coefficient and Data content. In some cases, the Coefficient content must be

derived using tools provided in Cirrus Logic

’s WISCE™ evaluation board control software.

Details of how to load the firmware configuration onto the WM8281 are described below. Note that the

WISCE evaluation board control software provides support for easy loading of Program, Coefficient

and Data content onto the WM8281. Please contact your local Cirrus Logic representative for more

details of the WISCE evaluation board control software.

After loading the DSP firmware, the DSP functions must be enabled using the associated register

control fields.

The audio signal paths connecting to/from the DSP processing blocks are configured as described in

the “Digital Core” section. Note that the DSP firmware must be loaded and enabled before audio

signal paths can be enabled.

DSP FIRMWARE MEMORY CONTROL

The DSP firmware memory is programmed by writing to the registers referenced in Table 26. Note

that the DSP clock must be configured and enabled for the respective DSP block to support read/write

access to these registers.

The WM8281 Program, Coefficient and Data register memory space is described in Table 26. See

“Register Map” for a definition of these register addresses. The shared DSP2/DSP3 memory space is

implemented at two different register address locations; note that reading or writing at either address

will access the same memory data.

If multiple DSPs write to a shared memory address at the same time, then the address at which the

collision occurred will be reported in the DSP3_DUALMEM_COLLISION_ADDR register. Note that

this field is coded in 24-bit DSP data word units, and is defined relative to the base address of the

applicable shared memory area.

The DSP memory controller provides an input to the Interrupt Controller circuit. An interrupt event is

triggered if a memory collision occurs. (Note that the DSP software should be written to ensure this

never happens; the interrupt is intended for development purposes only.)

See “Interrupts” for more

details of the Interrupt event handling.

The Program firmware parameters are formatted as 40-bit words. For this reason, 3 x 16-bit register

addresses are required for each 40-bit word.

The Coefficient and Data firmware parameters are formatted as 24-bit words. For this reason, 2 x 16-

bit register addresses are required for each 24-bit word.

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