WM8281ECSSLASHR datasheet(126/392 Pages) CIRRUS

126 / 392 page

WM8281

126

Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4612

(1204h)

DSP2

Status 1

DSP2_RAM_RD

DSP2 Memory Status

0 = Not ready

1 = Ready

Note - DSP2 memory should not be

accessed until this bit has been set.

R4614

(1206h)

DSP2

Status 3

3:1

DSP2_CLK_SEL

_STS [2:0

000

DSP2 Clock Frequency

(Read only, Only valid when the

respective DSP Clock is enabled)

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 73.728MHz (67.7376MHz)

101 = 98.304MHz (90.3168MHz)

110 = 147.456MHz (135.4752MHz)

111 = Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only (ie.

SAMPLE_RATE_n = 01XXX).

DSP2_CLK_AVAI

DSP2 Clock Availability

(Read only)

0 = No Clock

1 = Clock Available

Note

– this bit exists for legacy software

support only; it is not recommended for

future designs, as the readback may be

unreliable on the latest device

architectures.

R4864

(1300h)

DSP3

Control 1

DSP3_MEM_EN

DSP3 Memory Control

0 = DSP3 memory is cleared when

DSP3_SYS_ENA=0, and during Hardware

Reset or Software Reset.

1 = DSP3 memory is retained when

DSP3_SYS_ENA=0. DSP3 memory is

retained during Hardware Reset and

Software Reset.

DSP3_SYS_ENA

DSP3 Clock Enable

0 = Disabled

1 = Enabled

The DSP3 Clock must be enabled for

DSP3 firmware register access, code

execution, or DMA operation.

The DSP3 Core must be reset (by writing

DSP3_CORE_ENA=0) when disabling the

DSP3 Clock.

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