WM8281ECSSLASHR datasheet(124/392 Pages) CIRRUS

124 / 392 page

WM8281

124

Rev 4.0

When DSPn_MEM_ENA = 0, the DSP firmware memory is disabled (and the contents lost) when

DSPn_SYS_ENA = 0. It is also disabled during Hardware Reset and Software Reset. Power

consumption is reduced when the memory is disabled, but the DSP firmware must then be reloaded

when required.

Note that the DSP firmware memory is always cleared under Power-On Reset (POR)

and ‘Sleep’

mode conditions.

See the “Applications Information” section for a summary of the WM8281 memory

reset conditions.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4352

(1100h)

DSP1

Control 1

DSP1_MEM_EN

DSP1 Memory Control

0 = DSP1 memory is cleared when

DSP1_SYS_ENA=0, and during Hardware

Reset or Software Reset.

1 = DSP1 memory is retained when

DSP1_SYS_ENA=0. DSP1 memory is

retained during Hardware Reset and

Software Reset.

DSP1_SYS_ENA

DSP1 Clock Enable

0 = Disabled

1 = Enabled

The DSP1 Clock must be enabled for

DSP1 firmware register access, code

execution, or DMA operation.

The DSP1 Core must be reset (by writing

DSP1_CORE_ENA=0) when disabling the

DSP1 Clock.

R4353

(1101h)

DSP1

Clocking 1

2:0

DSP1_CLK_SEL

[2:0]

000

DSP1 Clock Frequency Select

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 73.728MHz (67.7376MHz)

101 = 98.304MHz (90.3168MHz)

110 = 147.456MHz (135.4752MHz)

111 = Reserved

The DSP1 Clock must be less than or

equal to the SYSCLK frequency. The

frequencies must also be integer-related

(eg. divide by 1, 2, 3 etc.).

The frequencies in brackets apply for

44.1kHz-related sample rates only (ie.

SAMPLE_RATE_n = 01XXX).

R4356

(1104h)

DSP1

Status 1

DSP1_RAM_RD

DSP1 Memory Status

0 = Not ready

1 = Ready

Note - DSP1 memory should not be

accessed until this bit has been set.

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