WM8281ECSSLASHR datasheet(123/392 Pages) CIRRUS

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WM8281

Rev 4.0

123

DESCRIPTION

DSP MEMORY SIZE

DSP1

Program memory

10_0000h to 10_5FFFh

(24576 registers)

8k x 40-bit words

Coefficient memory

18_0000h to 18_1FFFh

(8192 registers)

4k x 24-bit words

X Data memory

19_0000h to 19_7FFFh

(32768 registers)

16k x 24-bit words

Y Data memory

1A_8000h to 1A_9FFFh

(8192 registers)

4k x 24-bit words

DSP2

Program memory

20_0000h to 20_EFFFh

(61440 registers)

20k x 40-bit words

Coefficient memory

28_0000h to 28_1FFFh

(8192 registers)

4k x 24-bit words

X Data memory

29_0000h to 29_BFFFh

(49152 registers)

24k x 24-bit words

X Data memory

(Shared DSP2/DSP3)

2A_6000h to 2A_7FFFh

(8192 registers)

4k x 24-bit words

Y Data memory

2A_8000h to 2B_3FFFh

(49152 registers)

24k x 24-bit words

DSP3

Program memory

30_0000h to 30_EFFFh

(61440 registers)

20k x 40-bit words

Coefficient memory

38_0000h to 38_1FFFh

(8192 registers)

4k x 24-bit words

X Data memory

39_0000h to 3A_1FFFh

(73728 registers)

36k x 24-bit words

X Data memory

(Shared DSP2/DSP3)

3A_6000h to 3A_7FFFh

(8192 registers)

4k x 24-bit words

Y Data memory

3A_8000h to 3B_3FFFh

(49152 registers)

24k x 24-bit words

DSP4

Program memory

40_0000h to 40_5FFFh

(24576 registers)

8k x 40-bit words

Coefficient memory

48_0000h to 48_1FFFh

(8192 registers)

4k x 24-bit words

X Data memory

49_0000h to 49_7FFFh

(32768 registers)

16k x 24-bit words

Y Data memory

4A_8000h to 4A_9FFFh

(8192 registers)

4k x 24-bit words

Table 26 DSP Program, Coefficient and Data Registers

Clocking is required for any functionality of the DSP processing blocks, including any register

read/write operations associated with DSP firmware loading.

The clock source for each DSP is derived from SYSCLK, which must also be enabled. See “Clocking

and Sample Rates

” for details of how to configure SYSCLK.

The DSP clock frequency is selected using the DSPn_CLK_SEL register. Note that the DSP clock

frequency must be less than or equal to the SYSCLK frequency. The frequencies must be integer-

related (eg. divide by 1, 2, 3 etc.).

The clock source for each DSP block is enabled using DSPn_SYS_ENA

(where ‘n’ identifies the

applicable DSP processing block 1, 2, 3 or 4). The clock must be enabled before (or simultaneous to)

enabling the respective DSP Core or DMA channels. The clock must be disabled after (or

simultaneous to) disabling the DSP Core and DMA channels.

The DSPn_CLK_SEL_STS fields provide readback of the clock frequency for the respective DSP

cores. These can be used to confirm the clock frequency, in cases where code execution has a

minimum clock frequency requirement. The DSPn_CLK_SEL_STS field is only valid when the

respective DSP Clock is enabled; typical typical usage of this field would be for the DSP core itself to

readback the clock status, and to take action as applicable (in particular, if the available clock does

not meet the application requirements).

The DSPn_RAM_RDY status bits indicate when the respective DSP firmware memory registers are

ready for read/write access. The respective DSP memories should not be accessed until this bit has

been set.

The DSP RAM Ready flags are inputs to the Interrupt control circuit and can be used to trigger an

interrupt event -

see “Interrupts”.

The DSP RAM Ready flags can be output directly on a GPIO pin as an external indication of the DSP

RAM Status. S

ee “General Purpose Input / Output” to configure a GPIO pin for this function.

Under default register conditions, the DSP firmware memory contents are retained if the respective

clock is disabled, and also during Hardware Reset and Software Reset; this is selectable using the

DSPn_MEM_ENA register bits, as described below.

When DSPn_MEM_ENA = 1 (default), the DSP firmware memory is retained when the DSP clock is

disabled (ie. when DSPn_SYS_ENA = 0). It is also retained during Hardware Reset and Software

Reset, provided DCVDD is held above its reset threshold.

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