WM8281ECSSLASHR datasheet(136/392 Pages) CIRRUS

136 / 392 page

WM8281

136

Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4916

(1334h)

DSP3

RDMA

Config 1

5:0

DSP3_RDMA_C

HANNEL_ENABL

E [5:0]

00h

DSP3 RDMA Channel Enable

There are 6 RDMA channels; each bit of

this field enables the respective RDMA

channel.

Each bit is coded as:

0 = Disabled

1 = Enabled

R4917

(1335h)

DSP3

RDMA

Offset 1

5:0

DSP3_RDMA_C

HANNEL_OFFSE

T [5:0]

00h

DSP3 RDMA Channel Offset

There are 6 RDMA channels; each bit of

this field offsets the Start Address of the

respective RDMA channel.

Each bit is coded as:

0 = No offset

1 = Offset by 8000h

R5125

(1405h)

DSP4

Status 2

DSP4_PING_FU

DSP4 WDMA Ping Buffer Status

0 = Not Full

1 = Full

DSP4_PONG_FU

DSP4 WDMA Pong Buffer Status

0 = Not Full

1 = Full

7:0

DSP4_WDMA_A

CTIVE_CHANNE

LS [7:0]

00h

DSP4 WDMA Channel Status

There are 8 WDMA channels; each bit of

this field indicates the status of the

respective WDMA channel.

Each bit is coded as:

0 = Inactive

1 = Active

R5136

(1410h)

R5143

(1417h)

15:0

DSP4_START_A

DDRESS_WDMA

_BUFFER_n

[15:0]

0000h

DSP4 WDMA Channel n Start Address

Bit [15] = Memory select

0 = X Data memory

1 = Y Data memory

Bits [14:0] = Address select

The address is defined relative to the base

address of the applicable data memory.

The LSB represents one 24-bit DSP

memory word.

Note that the start address is also

controlled by the respective

DSP4_WDMA_CHANNEL_OFFSET bit.

R5152

(1420h)

R5157

(1425h)

15:0

DSP4_START_A

DDRESS_RDMA

_BUFFER_n

[15:0]

0000h

DSP4 RDMA Channel n Start Address

Bit [15] = Memory select

0 = X Data memory

1 = Y Data memory

Bits [14:0] = Address select

The address is defined relative to the base

address of the applicable data memory.

The LSB represents one 24-bit DSP

memory word.

Note that the start address is also

controlled by the respective

DSP4_RDMA_CHANNEL_OFFSET bit.

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