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WM8281ECS/R Scheda tecnica(PDF) 132 Page - Cirrus Logic

Il numero della parte WM8281ECS/R
Spiegazioni elettronici  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 132 Page - Cirrus Logic

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WM8281
132
Rev 4.0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4357
(1105h)
DSP1
Status 2
15
DSP1_PING_FU
LL
0
DSP1 WDMA Ping Buffer Status
0 = Not Full
1 = Full
14
DSP1_PONG_FU
LL
0
DSP1 WDMA Pong Buffer Status
0 = Not Full
1 = Full
7:0
DSP1_WDMA_A
CTIVE_CHANNE
LS [7:0]
00h
DSP1 WDMA Channel Status
There are 8 WDMA channels; each bit of
this field indicates the status of the
respective WDMA channel.
Each bit is coded as:
0 = Inactive
1 = Active
R4368
(1110h)
to
R4375
(1117h)
15:0
DSP1_START_A
DDRESS_WDMA
_BUFFER_n
[15:0]
0000h
DSP1 WDMA Channel n Start Address
Bit [15] = Memory select
0 = X Data memory
1 = Y Data memory
Bits [14:0] = Address select
The address is defined relative to the base
address of the applicable data memory.
The LSB represents one 24-bit DSP
memory word.
Note that the start address is also
controlled by the respective
DSP1_WDMA_CHANNEL_OFFSET bit.
R4384
(1120h)
to
R4389
(1125h)
15:0
DSP1_START_A
DDRESS_RDMA
_BUFFER_n
[15:0]
0000h
DSP1 RDMA Channel n Start Address
Bit [15] = Memory select
0 = X Data memory
1 = Y Data memory
Bits [14:0] = Address select
The address is defined relative to the base
address of the applicable data memory.
The LSB represents one 24-bit DSP
memory word.
Note that the start address is also
controlled by the respective
DSP1_RDMA_CHANNEL_OFFSET bit.
R4400
(1130h)
DSP1
WDMA
Config 1
13:0
DSP1_WDMA_B
UFFER_LENGTH
[13:0]
0000h
DSP1 DMA Buffer Length
Selects the amount of data transferred in
each WDMA channel. The LSB represents
one 24-bit DSP memory word.
R4401
(1131h)
DSP1
WDMA
Config 2
7:0
DSP1_WDMA_C
HANNEL_ENABL
E [7:0]
00h
DSP1 WDMA Channel Enable
There are 8 WDMA channels; each bit of
this field enables the respective WDMA
channel.
Each bit is coded as:
0 = Disabled
1 = Enabled



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