WM8281ECSSLASHR datasheet(133/392 Pages) CIRRUS

133 / 392 page

WM8281

Rev 4.0

133

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4402

(1132h)

DSP1

WDMA

Offset 1

7:0

DSP1_WDMA_C

HANNEL_OFFSE

T [7:0]

00h

DSP1 WDMA Channel Offset

There are 8 WDMA channels; each bit of

this field offsets the Start Address of the

respective WDMA channel.

Each bit is coded as:

0 = No offset

1 = Offset by 8000h

R4404

(1134h)

DSP1

RDMA

Config 1

5:0

DSP1_RDMA_C

HANNEL_ENABL

E [5:0]

00h

DSP1 RDMA Channel Enable

There are 6 RDMA channels; each bit of

this field enables the respective RDMA

channel.

Each bit is coded as:

0 = Disabled

1 = Enabled

R4405

(1135h)

DSP1

RDMA

Offset 1

5:0

DSP1_RDMA_C

HANNEL_OFFSE

T [5:0]

00h

DSP1 RDMA Channel Offset

There are 6 RDMA channels; each bit of

this field offsets the Start Address of the

respective RDMA channel.

Each bit is coded as:

0 = No offset

1 = Offset by 8000h

R4613

(1205h)

DSP2

Status 2

DSP2_PING_FU

DSP2 WDMA Ping Buffer Status

0 = Not Full

1 = Full

DSP2_PONG_FU

DSP2 WDMA Pong Buffer Status

0 = Not Full

1 = Full

7:0

DSP2_WDMA_A

CTIVE_CHANNE

LS [7:0]

00h

DSP2 WDMA Channel Status

There are 8 WDMA channels; each bit of

this field indicates the status of the

respective WDMA channel.

Each bit is coded as:

0 = Inactive

1 = Active

R4624

(1210h)

R4631

(1217h)

15:0

DSP2_START_A

DDRESS_WDMA

_BUFFER_n

[15:0]

0000h

DSP2 WDMA Channel n Start Address

Bit [15] = Memory select

0 = X Data memory

1 = Y Data memory

Bits [14:0] = Address select

The address is defined relative to the base

address of the applicable data memory.

The LSB represents one 24-bit DSP

memory word.

Note that the start address is also

controlled by the respective

DSP2_WDMA_CHANNEL_OFFSET bit.

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