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WM8281ECS/R Scheda tecnica(PDF) 134 Page - Cirrus Logic |
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WM8281ECS/R Scheda tecnica(HTML) 134 Page - Cirrus Logic |
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134 / 392 page ![]() WM8281 134 Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4640 (1220h) to R4645 (1225h) 15:0 DSP2_START_A DDRESS_RDMA _BUFFER_n [15:0] 0000h DSP2 RDMA Channel n Start Address Bit [15] = Memory select 0 = X Data memory 1 = Y Data memory Bits [14:0] = Address select The address is defined relative to the base address of the applicable data memory. The LSB represents one 24-bit DSP memory word. Note that the start address is also controlled by the respective DSP2_RDMA_CHANNEL_OFFSET bit. R4656 (1230h) DSP2 WDMA Config 1 13:0 DSP2_WDMA_B UFFER_LENGTH [13:0] 0000h DSP2 DMA Buffer Length Selects the amount of data transferred in each WDMA channel. The LSB represents one 24-bit DSP memory word. R4657 (1231h) DSP2 WDMA Config 2 7:0 DSP2_WDMA_C HANNEL_ENABL E [7:0] 00h DSP2 WDMA Channel Enable There are 8 WDMA channels; each bit of this field enables the respective WDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4658 (1232h) DSP2 WDMA Offset 1 7:0 DSP2_WDMA_C HANNEL_OFFSE T [7:0] 00h DSP2 WDMA Channel Offset There are 8 WDMA channels; each bit of this field offsets the Start Address of the respective WDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4660 (1234h) DSP2 RDMA Config 1 5:0 DSP2_RDMA_C HANNEL_ENABL E [5:0] 00h DSP2 RDMA Channel Enable There are 6 RDMA channels; each bit of this field enables the respective RDMA channel. Each bit is coded as: 0 = Disabled 1 = Enabled R4661 (1235h) DSP2 RDMA Offset 1 5:0 DSP2_RDMA_C HANNEL_OFFSE T [5:0] 00h DSP2 RDMA Channel Offset There are 6 RDMA channels; each bit of this field offsets the Start Address of the respective RDMA channel. Each bit is coded as: 0 = No offset 1 = Offset by 8000h R4869 (1305h) DSP3 Status 2 15 DSP3_PING_FU LL 0 DSP3 WDMA Ping Buffer Status 0 = Not Full 1 = Full 14 DSP3_PONG_FU LL 0 DSP3 WDMA Pong Buffer Status 0 = Not Full 1 = Full |
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