WM8281ECSSLASHR datasheet(243/392 Pages) CIRRUS

243 / 392 page

WM8281

Rev 4.0

243

CONTROL INTERFACE ERROR STATUS OUTPUT

GPn_FN = 16h.

The WM8281 is controlled by writing to registers through a 2-wire (I2C) or 4-wire (SPI) serial control

interface, as

described in the “Control Interface” section. The SLIMbus interface also supports

read/write access to the control registers, as described in the “SLIMbus Interface Control” section.

The WM8281 performs automatic checks to confirm if a register access is successful. Register access

will be unsuccessful if an invalid register address is selected. Read/write access to the DSP firmware

memory will be unsuccessful if the associated clocking is not enabled. If an invalid or unsuccessful

The Control Interface Error signal may be output directly on a GPIO pin by setting the respective

GPIO registers as described in “GPIO Control”.

The Control Interface Error signal is an input to the Interrupt Controller circuit. An interrupt event is

triggered on the rising edge of the Control Interface Error signal. The associated interrupt bit is latched

once set; it can be polled at any time or used to con

trol the IRQ signal. See “Interrupts” for more

details of the Interrupt event handling.

SYSTEM CLOCKS ENABLE STATUS OUTPUT

GPn_FN = 4Bh, 4Ch.

The WM8281 requires a system clock (SYSCLK) for its internal functions and to support the

input/output signal paths. The WM8281 can support two independent clock domains, with selected

functions referenced to the ASYNCCLK clock domain. See “Clocking and Sample Rates” for details of

these clocks.

The SYSCLK_ENA and ASYNC_CLK_ENA registers (see Table 101) control the SYSCLK and

ASYNCCLK signals respectively.

When ‘0’ is written to these registers, the host processor must wait

until the WM8281 has shut down the associated functions before issuing any other register write

commands.

The SYSCLK Enable and ASYNCCLK Enable status may be output directly on a GPIO pin by setting

the respective GPIO registers as described in “GPIO Control”.

The SYSCLK Enable and ASYNCCLK Enable signals are inputs to the Interrupt Controller circuit. An

interrupt event is triggered when the respective clock functions have been shut down. The associated

interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See

“Interrupts” for more details of the Interrupt event handling.

WM8281ECS/R Scheda tecnica(PDF) 243 Page - Cirrus Logic