WM8281ECSSLASHR datasheet(240/392 Pages) CIRRUS

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WM8281

240

Rev 4.0

GPN_FN

DESCRIPTION

COMMENTS

2Fh

HPOUT1L Enable Status

A short pulse is output when the respective

control sequence has completed.

30h

HPOUT1R Enable Status

31h

HPOUT2L Enable Status

32h

HPOUT2R Enable Status

33h

HPOUT3L Enable Status

34h

HPOUT3R Enable Status

Table 92 Headphone Enable Status Indications

BOOT DONE STATUS OUTPUT

GPn_FN = 44h.

The WM8281 executes a user-configurable Boot Sequence following Power-On Reset (POR),

Hardware Reset, Software Reset or Wake-Up (from Sleep mode). Control register writes should not

be attempted while the Boot Sequence is running.

For details of the Boot Sequence, see “Control Write Sequencer”.

The BOOT_DONE_STS register bit (see Table 128) indicates the status of the Boot Sequence.

(When BOOT_DONE_STS=1, then the Boot Sequence is complete.)

A logic signal from the Boot Sequence function may be output directly on a GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a short

pulse duration (approx. 100ns) when the Boot Sequence has completed. To output this signal, the

Boot Sequence must be programmed to configure a GPIO pin for this function. Note that, under

default register conditions, completion of the Boot Sequence is indicated via the Interrupt circuit.

The BOOT_DONE_STS signal is also an input to the Interrupt Controller circuit. An interrupt event is

triggered on the rising edge of this signal. The associated interrupt bit is latched once set; it can be

polled at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt

event handling.

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT

GPn_FN = 1Ah, 1Bh.

The WM8281 maintains a flag indicating the lock status of the Asynchronous Sample Rate Converters

(ASRCs)

, which may be used to control other events if required. See “Digital Core” for more details of

the ASRCs.

The ASRC Lock signals may be output directly on a GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”.

The ASRC Lock signals are inputs to the Interrupt control circuit. An interrupt event is triggered on the

rising and falling edges of the ASRC Lock signals. The associated interrupt bits are latched once set;

they can be polled at any time or used to control the IRQ signal. See “Interrupts” for more details of

the Interrupt event handling.

ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) CONFIGURATION ERROR

STATUS OUTPUT

GPn_FN = 1Ch.

The WM8281 performs automatic checks to confirm that the ASRCs are configured with valid settings.

Invalid settings include conditions where one of the associated sample rates is higher than 48kHz. If

an invalid ASRC configuration is detected, this can be indicated using the GPIO and/or Interrupt

functions.

The ASRC Configuration Error signal may be output directly on a GPIO pin by setting the respective

GPIO registers as described

in “GPIO Control”.

The ASRC Configuration Error signal is an input to the Interrupt Controller circuit. An interrupt event is

triggered on the rising edge of the ASRC Configuration Error signal. The associated interrupt bit is

latched once set; it

can be polled at any time or used to control the IRQ signal. See “Interrupts” for

more details of the Interrupt event handling.

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