WM8281ECSSLASHR datasheet(244/392 Pages) CIRRUS

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WM8281

244

Rev 4.0

CLOCKING ERROR STATUS OUTPUT

GPn_FN = 0Ah, 0Bh, 17h, 18h, 19h, 27h, 2Dh, 2Eh.

The WM8281 performs automatic checks to confirm that the system clocks are correctly configured

according to the commanded functionality. An invalid configuration is one where there are insufficient

clock cycles to support the digital processing required by the commanded signal paths.

An Underclocked Error condition is where there are insufficient clock cycles for the requested

functionality, and increasing the SYSCLK or ASYNCCLK frequency (as applicable) should allow the

selected configuration to be supported.

An Overclocked Error condition is where the requested functionality cannot be supported, as the

clocking requirements of the requested configuration exceed the device limits.

The system clocks (SYSCLK and, where applicable, ASYNCCLK) must be enabled before any signal

path is enabled. If an attempt is made to enable a signal path, and there are insufficient clock cycles

to support that path, then the attempt will be unsuccessful. Note that any signal paths that are already

active will not be affected under these circumstances.

The Clocking Error signals may be output directly on a GPIO pin by setting the respective GPIO

registers as described in “GPIO Control”. The Clocking Error conditions are described in Table 94.

The Clocking Error signals are inputs to the Interrupt Controller circuit. An interrupt event is triggered

on the rising and falling edges of the Clocking Error signals. The associated interrupt bits are latched

once set; they can be polled at any time or used to control the IR

Q signal. See “Interrupts” for more

details of the Interrupt event handling.

GPN_FN

DESCRIPTION

COMMENTS

0Ah

SYSCLK Underclocked

Indicates insufficient SYSCLK cycles for the

commanded functionality.

0Bh

ASYNCCLK

Underclocked

Indicates insufficient ASYNCCLK cycles for the

commanded functionality.

17h

ADC Overflow Error

Indicates an overflow condition in the input signal paths.

18h

ADC CIC Error

Indicates a CIC error condition in the input signal paths.

19h

ADC FIFO Error

Indicates a FIFO error condition in the input signal

paths.

27h

Mixer Dropped Sample

Error

Indicates a dropped sample in the digital core mixer

function.

2Dh

Underclocked Error

Indicates insufficient SYSCLK or ASYNCCLK cycles for

one or more of the selected signal paths or signal

processing functions. Increasing the SYSCLK or

ASYNCCLK frequency (as applicable) should allow the

selected configuration to be supported.

Status bits associated with specific sub-systems provide

further de-bug capability.

The INnx_ENA_STS bits in register R769 indicate the

status of each of the input (analogue or digital

microphone) signal paths.

The OUTnx_ENA_STS bits in registers R1025 and

R1030 indicate the status of each of the output

(Headphone, Speaker or PDM) signal paths.

The ASRCnx_ENA_STS bits in register R3809 indicate

the status of each of the ASRC signal paths.

The FX_STS field in register R3585 indicates the status

of each of the Effects (EQ, DRC or LHPF) signal paths.

The *MIX_STSn fields in registers R1600 to R3000

indicate the status of each of the Digital Core mixer

signal paths.

The ISRCn and AIFn functions are also inputs to the

Underclocked Error status indication, but there are no

specific _STS register bits associated with these.

2Eh

Overclocked Error

Indicates that an unsupported device configuration has

been attempted, as the clocking requirements of the

requested configuration exceed the device limits.

Table 94 Clocking Error Status Indications

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