WM8281ECSSLASHR datasheet(242/392 Pages) CIRRUS

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WM8281

242

Rev 4.0

DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT

GPn_FN = 1Dh, 1Eh, 1Fh, 20h, 21h, 22h, 23h, 24h, 25h, 26h.

The Dynamic Range Control (DRC) circuits provide status outputs, which may be used to control

other events if required.

The DRC status flags may be output directly on a GPIO pin by setting the respective GPIO registers

as described in “GPIO Control”. The DRC status outputs are described in Table 93.

See “Digital Core” for more details of the DRC.

GPN_FN

DESCRIPTION

COMMENTS

1Dh

DRC1 Signal Detect

Indicates a signal is present on the respective DRC

path. The threshold level is configurable (see Table 15).

1Eh

DRC1 Anti-Clip Active

Indicates the DRC anti-clip function has been triggered;

the DRC gain is decreasing in response to a rising

signal level.

1Fh

DRC1 Decay Active

Indicates that the DRC gain is increasing in response to

a low-level signal input.

20h

DRC1 Noise Gate Active

Indicates that the DRC noise gate has been triggered;

an idle signal condition has been detected.

21h

DRC1 Quick Release

Active

Indicates that the DRC quick-release function has been

triggered; the DRC gain is increasing rapidly following

detection of a short transient peak.

22h

DRC2 Signal Detect

Description as above.

23h

DRC2 Anti-Clip Active

Description as above.

24h

DRC2 Decay Active

Description as above.

25h

DRC2 Noise Gate Active

Description as above.

26h

DRC2 Quick Release

Active

Description as above.

Table 93 Dynamic Range Control (DRC) Status Indications

CONTROL WRITE SEQUENCER STATUS OUTPUT

GPn_FN = 15h.

The WM8281 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write

operations in response to a simple trigger event.

See “Control Write Sequencer” for details of the

Control Write Sequencer.

The WSEQ_BUSY register bit (see Table 121) indicates the status of the Control Write Sequencer.

When WSEQ_BUSY=1, this indicates that one or more Write Sequence operations are in progress or

are queued for sequential execution.

A logic signal from the Write Sequencer function may be output directly on a GPIO pin by setting the

respective GPIO registers as described in “GPIO Control”. This logic signal is set high for a short

pulse duration (approx. 100ns) whenever the Write Sequencer has completed all scheduled

sequences, and there are no more pending operations

The Write Sequencer status is an input to the Interrupt control circuit. An interrupt event is triggered

on completion of a Control Sequence. The associated interrupt bit is latched once set; it can be polled

at any time or used to control the IRQ signal. See “Interrupts” for more details of the Interrupt event

handling.

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