AD9546SLASHPCBZ datasheet(107/205 Pages) AD

107 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 107 of 205

MODULATION PERIOD

The modulation period is the interval between modulation events

(see Figure 75). To control the modulation period parameter,

use the 28-bit unsigned integer (modulation counter) in the

counter value carries units of the period of the output clock of

the associated Q divider.

The modulation counter value must be greater than or equal to six.

Table 71. Modulation Period Address Ranges

Modulator

Q0A

0x10C2 to 0x10C5

Q0B

0x10C6 to 0x10C9

Q0C

0x10CA to 0x10CD

Q1A

0x14C2 to 0x14C5

Q1B

0x14C6 to 0x14C9

The three lower addresses for each Q divider in Table 71 carry

the 24 LSBs of the 28-bit integer, and Bits[3:0] of the upper

address carry the four MSBs of the 28-bit integer (Bits[7:4] are

unused).

The modulation period (tMOD) depends on the input clock

frequency (fIN), the divide ratio of the associated Q divider, and

the modulation counter value.

tMOD = Modulation Counter × (Qxy/fIN)

(4)

Suppose the input clock to Q Divider Q0A comes from APLL0

with its VCO operating at 2.38 GHz. Because the VCO drives

a divide-by-2 block prior to the Q divider clock input, the

Q divider input frequency (fIN) is 1.19 GHz. Find the value of

the modulation counter value required to yield a modulation

period (tMOD) of 1 ms (0.001 sec) for a Q divide ratio of 107.5.

Substituting the appropriate values into Equation 4 yields

10−3 = Modulation Counter × (107.5/(1.19 × 109))

Therefore,

Modulation Counter = 11,070 (nearest integer)

= 0x 0000 2B3E (hexadecimal)

The desired modulation period (tMOD) is 1 ms. The modulation

counter value must be an integer. However, it is not always

possible to produce the desired modulation period exactly. In

this example, the actual tMOD value is 1.0000210084 ms (per

Equation 4).

BALANCED AND UNBALANCED MODULATION

Modulation consists of periodic modulation events occurring at

regular intervals, tMOD, with a single modulation event spanning

two output clock cycles of the Q divider associated with the

modulator. The modulator applies the specified pulse width

variation (per the modulation step and modulation counter) to

one or both clock cycles of the modulation event. Modulation

of both clock cycles constitutes balanced modulation, whereas

modulation of only one clock cycle constitutes unbalanced

modulation.

With balanced modulation, the modulator applies opposite

polarity to the modulation steps of the two consecutive cycles

of the modulation event (see Figure 76). As such, balanced

modulation maintains the average dc level of the waveform at

its nominal 50% amplitude point.

With unbalanced modulation, the modulator applies the

modulation step (Δt) to only the first pulse of the modulation

event, leaving the second pulse unaltered (see Figure 77) and

resulting in a waveform with a dc level slightly less than its

nominal 50% amplitude point.

To select between unbalanced and balanced modulation, use

Bit 2 per the register address in Table 70 for a given Q divider.

Logic 0 (default) selects balanced modulation, whereas Logic 1

selects unbalanced modulation.

By default, the first pulse of a modulation event has −Δt (and

the second pulse +Δt if balance modulation is in effect).

However, the user can force alternate polarity, where the first

pulse of a modulation event has +Δt (and the optional second

pulse has −Δt). Polarity control is via Bit 1 per the register

address in Table 70 for a given Q divider. Logic 0 (default)

applies negative polarity to Δt for the first pulse of a

modulation event, whereas Logic 1 applies positive polarity to

Δt for the first pulse (see Figure 78), which causes a positive shift

in dc offset in the case of unbalanced modulation.

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