AD9546SLASHPCBZ datasheet(109/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 109 of 205

MODULATION SYNCHRONIZATION

The periodic modulation events produced by the modulators

are useful as timing markers for synchronization purposes.

Both the balanced and unbalanced modulation schemes use

two Q divider output cycles to define a modulation event (see

Figure 76 and Figure 77). In the case of unbalanced

modulation, the second cycle is unaltered but is still part of the

modulation event. As such, the first rising edge of the Q divider

output following the second modulated cycle marks the base

edge for synchronization purposes (see Figure 79).

The synchronization information available from the

modulators requires the use of a secondary signal path. This

path is the reason the modulators have SIGx and SNCx output

signals. The SIGx signals are the modulated waveforms that

ultimately propagate to the distribution output pins.

The SNCx signals are internal only and carry synchronization

information attached to the modulation events corresponding

with the associated SIGx signal (for example, SNCA associates

with SIGA). The SNCx signal is a pulse coincident with the base

edge of the corresponding SIGx signal, as shown in Figure 80.

As shown in Figure 68, the SNCx signals route to the DPLL via

the hitless/zero delay feedback and synchronization block of

the N shot/PRBS controller. The SNCx signals provide

synchronization to the N divider of the corresponding DPLL

channel. The device automatically selects the appropriate SNCx

signal for the Q divider chosen for feedback (when modulation is

in effect for that particular Q divider). The SNCx selection

depends on Bits[4:2], the 3-bit tag mode bit field in the registers

associated with tag modes in the translation profiles (see the

Translation Profiles section) per Table 72.

Table 72. Tag Mode Register Address

Translation Profile

0.0

0x1203

0.1

0x1223

0.2

0x1243

0.3

0x1263

0.4

0x1283

0.5

0x12A3

1.0

0x1603

1.1

0x1623

1.2

0x1643

1.3

0x1663

1.4

0x1683

1.5

0x16A3

Because the SNCx signal identifies the modulation base edge,

the user can synchronize the DPLL N divider with a specific

synchronization edge per Figure 80. To specify a synchronization

edge (0, 1, 2, or 3) for the N divider, use Bits[1:0] of

decimal value of the bit pair corresponds to the desired

synchronization edge in Figure 80.

The choice of synchronization edge (0, 1, 2, or 3) puts an

additional constraint on the value of the modulation counter

(see the Modulation Period section) as follows:

Modulation Counter ≥ Sync Edge + 7

TIME

MODULATION EVENT

BASE

EDGE

Figure 79. Modulation Synchronization Edges

TIME

SYNC EDGE

MODULATION

EVENT

MODULATION

EVENT

SYNC EDGE

SIGx

SNCx

MODULATION PERIOD

BASE

EDGE

BASE

EDGE

Figure 80. Modulation Synchronization

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