AD9546SLASHPCBZ datasheet(111/205 Pages) AD

111 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 111 of 205

DISTRIBUTION OUTPUT CLOCK SYNCHRONIZATION

SYNCHRONIZATION OVERVIEW

The AD9546 has a built in synchronization controller that

provides the user with a flexible and sophisticated means to

synchronize its multiple output clock signals. The synchronization

controller properly sequences internal events to ensure proper

synchronizing of the output clocks of the device.

There are three ways to trigger the synchronization sequence.

•

Manually (via Bit 3 of Register 0x2000, via Bit 3 of

via an op code in an EEPROM download, or via an Mx

pin)

•

Autoreconfiguration (changes to Q divider values)

•

Autosynchronization

Autosynchronization is the preferred option for output clock

synchronization.

A synchronization trigger event is channel specific, applying to

either PLL0 or PLL1. The exception is manual synchronization,

which can apply to both channels via Bit 3 of Register 0x2000.

Assertion of Bit 3 does not imply synchronization of both

channels relative to each other but causes a simultaneous triggering

of the synchronization process for both channels.

A synchronization trigger initiates the synchronization

sequence. Following a trigger event, the synchronization

controller checks whether Bit 2 of Register 0x10DB or Register

0x14DB is set. If so, the synchronization controller waits for a

hitless profile to become valid before muting all outputs (because

reference synchronization is only viable for zero delay/hitless

translation modes).

Next, the synchronization controller confirms that the output

drivers are muted and then puts the P dividers and Q dividers

in a reset state (for the controller to load new Q divider

configuration information, for example, a new divide ratio).

Then the synchronization controller again checks whether Bit 2

of Register 0x10DB or Register 0x14DB is set so the controller

can align the release of the output clocks with a rising edge of

the active reference. However, if Bit 2 of Register 0x10DB or

checks for release of manual synchronization (that is, a clearing

of Bit 3 of Register 0x2000, or Bit 3 of Register 0x2101 (for

PLL0) or Bit 3 of Register 0x2201 (for PLL1). The

synchronization controller also checks that the APLL indicates

calibrated and locked status before proceeding.

Next, the synchronization controller unmutes the output

drivers and releases the appropriate Q dividers from their reset

state. Finally, the synchronization controller returns to waiting

for a subsequent synchronization trigger.

The output clock synchronization sequence initiates only when

the system clock is locked and stable.

OUTPUT SIGNALS AFTER POWER-UP OR RESET

A particularly important aspect of the synchronization controller

involves the control of the output clocks following a device

power-up or reset. On power-up or reset, the synchronization

controller waits for a synchronization trigger before activating

the output clocks. Until a synchronization trigger occurs, the

synchronization controller holds all the distribution Q dividers

in a reset state, which prevents any clock signals from

appearing at the OUTxyN and OUTxyP pins. Therefore, the

user must initiate the synchronization sequence to have any

clock signals appear at the output.

MANUAL SYNCHRONIZATION TRIGGER

A manual synchronization trigger occurs when the user sets

one of three manual synchronization bits. Programming Bit 3 =

1 of Register 0x2000 initiates the synchronization sequence for

all the AD9546 output clocks. Alternatively, the user can

synchronize only those outputs associated with one of the PLL

channels by programming Bit 3 = 1 of Register 0x2101 for PLL0

or Bit 3 = 1 of Register 0x2201 for PLL1. The same

synchronization features available via these bits are also

available via any of the Mx pins configured as an input.

Setting any of the D3 bits causes the synchronization sequence

to execute up to the point just before unmuting all drivers. At

that point, the synchronization controller stalls, waiting for the

user to clear the appropriate manual synchronization bit. This

delay allows the user to update the Q divider ratios before the

controller unmutes the output drivers, which does not occur

until the user clears the relevant manual synchronization bit.

AUTORECONFIGURATION SYNCHRONIZATION

TRIGGER

An autoreconfiguration synchronization trigger occurs when

the user changes any of the Q divider ratios and subsequently

sets the IO update bit. However, the autoreconfiguration

synchronization trigger applies only after the synchronization

controller has already completed a synchronization sequence as

the result of a power-up (or reset). After a power-up (or reset)

synchronization sequence completes, any subsequent updates

to the Q divider ratios constitutes an autoreconfiguration

synchronization trigger.

Autoreconfiguration is a convenience feature, because it

synchronizes the outputs automatically when the user changes

one or more Q divider values and subsequently sets the IO

update bit. This feature alleviates the need to initiate a manual

synchronization trigger to change Q divider values. Be aware,

however, that changing a single Q divider value affects all the

clock signals of the corresponding PLL channel. Specifically,

changing the value of any Q0x (where x = A, AA, B, BB, C, or

CC) results in disturbing all the Output 0 clock outputs because

it initiates a synchronization sequence for those outputs.

Likewise, changing the value of any Q1x divider (where x = A,

AD9546/PCBZ Scheda tecnica(PDF) 111 Page - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 111 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL