AD9546SLASHPCBZ datasheet(110/205 Pages) AD

110 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 110 of 205

MODULATION TRIGGER

By default, when modulation is in effect for a given Q divider,

the modulator applies the modulation immediately. However, it

is also possible to delay modulation until triggered. To enable

this feature for a given Q divider, use Bit 3 in the register

address shown in Table 70. Logic 0 (default) disables the

triggering feature, whereas Logic 1 enables it.

When enabled, the modulators use the trigger and mode signals

originating within the N shot/PRBS controller (see Figure 68).

The mode behavior differs slightly from that of the N shot/PRBS

controller. Specifically, when N shot request mode (Bit 6 in

instead of the modulator continuously generating periodic

modulation events, it generates only five periodic modulation

events and then stops. Conversely, when N shot request mode

= 1, the modulator continuously generates modulation events

when the N shot request signal (see Figure 68) is Logic 1. This

behavior allows synchronous enable or disable of modulation

events without losing synchronization during modulation.

The modulators, like the N shot generators, provide a retimed

trigger option (see the N Shot Triggering section). However, in

the case of the modulators, retiming relates to modulation

events rather than the carrier clock edges associated with the Q

divider. By default, the retiming block retimes to the carrier

clock edges. To select retiming to modulation events, program

Bit 4 to Logic 1 in Register 0x10D6 (PLL0) or Register 0x14D6

(PLL1).

Q0A

Q0AA

Q0B

TRIGGER

SIGNAL

RETIMED

TRIGGER

N SHOT OUT0AP

N SHOT OUT0AN

N SHOT OUT0BP

TIME

3-OUTPUT CYCLE LATENCY

MINIMUM 48 Q DIVIDER INPUT HALF CYCLES

Figure 81. Trigger Retiming (with Q0AA as the Retiming Q Divider)

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