AD9546SLASHPCBZ datasheet(120/205 Pages) AD

120 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 120 of 205

When Bit 7 is Logic 0 (default), detection of a phase step causes

only the first event to occur. By initializing a new DPLL

acquisition sequence, the DPLL can take advantage of the fast

acquisition feature (see the DPLL Fast Acquisition Options

section), assuming it is active, which is helpful for very low loop

bandwidth applications. In addition, a new acquisition manages

the impact of the phase step by either building out the phase or

slewing to the new phase in a hitless manner.

When control Bit 7 is Logic 1, detection of a phase step causes

both events to occur. Because exceeding the phase step

threshold in this case implies an external switch to a new

reference, resetting the reference monitor forces it to establish

new reference statistics (see the Reference Monitor section).

The phase transient threshold detector provides the user with a

status indicator for the occurrence of a phase step detection via

Bit 0 of Register 0x3011 and Register 0x3016 (for PLL0 and

PLL1, respectively). Because these status indicators are latched

IRQ bits, the user must clear them via Bit 0 of Register 0x200C

and Register 0x2011 (for PLL0 and PLL1, respectively) to

obtain visibility of subsequent threshold violations detected by

the phase step detector (see the Interrupt Request (IRQ)

section).

Mitigating Phase Step Limit False Positives

When enabled, the phase transient threshold detector operates

continuously while the associated reference is the active

reference for the DPLL (DPLL0 or DPLL1), assuming the DPLL

is frequency locked. As such, any phase disturbance at the input

to the phase detector, including user induced phase adjustment

per the DPLL Phase Offset Control section and the Skew

Adjustment section, is subject to violating the threshold of the

phase transient threshold detector. To mitigate false triggering

of the phase transient threshold detector (when enabled) due to

intentional phase adjustments, the user can employ the phase

slew rate limiter (see the Phase Slew Rate Limit section).

The following formula relates the maximum phase slew rate

(MPSR) assigned to the phase slew rate limiter necessary to

prevent inadvertent triggering of the phase transient threshold

detector due to a user induced phase disturbance:

MPSR ≤ (P × f)/7

(16)

where:

P is the phase transient threshold detector limit (in ps).

f is the frequency (in Hz) at the input of the DPLL phase detector.

The inequality in Equation 16 ignores other contributors to

phase error such as jitter, frequency offset, and propagation

delay variation. Because MPSR in Equation 16 constitutes an

upper limit, it is recommended to use a lower value of MPSR to

provide margin (a 25% reduction is reasonable).

If the user has advance knowledge of the timing of an external

event such as the switching of the reference input clock source

via an external mux, rather than using the phase transient step

detector, a better solution is to invalidate the associated

reference manually (see the Invalidate section of the Reference

Monitor section). Manual reference invalidation imposes the

least impact on the steady state operation of the device. The

only steady state impact is that the validation timer of the

associated reference must be set to a duration that is longer

(with suitable margin) than the duration between the assertion

of the forced fault condition and the occurrence of the external

event.

SKEW ADJUSTMENT

Skew adjustment allows the user to associate a fixed phase

offset with a reference input, which is useful in applications

with redundant GNSS or GPS reference sources, for example.

That is, a user can have two or more GNSS/GPS sources that

have identical frequency but exhibit a fixed time offset due to a

mismatch between antenna cable lengths.

To activate the skew adjustment feature, use Bits[23:0] (signed)

of the appropriate source profile at the start address shown in

Table 78 plus an offset of 14 to 16 (decimal). Bits[23:0]

constitute the phase skew value. A phase skew value of zero

(default) disables the phase skew adjustment feature, whereas a

nonzero value serves to activate the phase skew adjustment

feature and define the desired phase skew in units of ps. The

time skew associated with phase skew value is given by the

following equation:

Time Skew = Phase Skew × 10−12

(17)

For example, determine the value of phase skew bit necessary

for a time skew of –35 ns. Solving Equation 17 for phase skew

yields the following:

Phase Skew = Time Skew/10−12

= (–35 × 10−9)/10−12

= –35,000

= 0x FF 7748 (hexadecimal)

INITIAL PHASE SKEW REFINEMENT STEPS

Whenever the AD9546 performs a reference switchover, it

performs an initial assessment of the time offset between the

old and new reference. The device does not use the phase of the

new reference to determine the phase offset but compares the

time stamps of the feedback TDC with the time stamps from

the TDC of the new reference (see Figure 87). This comparison

allows the device to insert an opposing time offset into the

servo loop of the DPLL, a phase buildout operation (see the

Frequency Translation Loops section).

For a phase buildout translation loop, initial phase offset

insertion is an essential component of a reference switch over

requiring phase buildout. However, the AD9546 also supports

hitless translation profiles, for which phase buildout is not

necessary. The AD9546 has the capability of initial phase offset

insertion to build out the initial phase offset for a hitless

switchover as well. By applying phase buildout at the start of a

hitless switchover, the AD9546 can significantly reduce the

time necessary to complete a hitless switchover acquisition.

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