AD9546SLASHPCBZ datasheet(117/205 Pages) AD

117 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 117 of 205

INTERNAL ZERO DELAY (HITLESS) MODE

Figure 84 shows the internal zero delay configuration. Internal

zero delay mode is a hitless mode (rather than phase buildout

operating mode), in which the AD9546 gradually changes the

output phase as DPLLx realigns to the phase of the new

reference. The user has some control over the magnitude of the

output disturbance via the phase slew limit of the AD9546 and

tuning word clamp features (see the Phase Slew Rate Limit

section and Tuning Word Offset Clamp section, respectively).

In internal zero delay mode, the feedback path of the PLL origi-

nates at the output of a user selected Q divider in the output

distribution section. The user selects the feedback Q divider

selection via the translation profile registers. To select the

feedback Q divider, use Bits[4:0] (unsigned integer) in the

plus an offset of 2 (decimal).

The decimal value of Bits[4:0] selects the Q divider per the

Internal Zero Delay column in Table 77. With DPLL N divider

set for integer only (that is, no fractional component—a

requirement for zero delay operation), the internal zero delay

configuration ensures no phase offset between the reference

TDC and the output of the user selected Q divider.

The frequency translation factor for internal zero delay mode is

REFx

OUTx

To provide true hitless operation, internal zero delay mode

requires a constraint on the relationship between fREFx and fOUTx.

Namely, fOUTx/fREFx must be an integer greater than or equal to 1.

The NCO, VCO, TDCs, and the APLL PFD inputs each have

specific frequency limits. The following formulas relate fNCO,

fVCO, fTDC, and fPFD to fREFx, fOUTx, and divider values. Note that

each formula has two solutions: one with respect to the input

frequency (fREFx) and the other with respect to the output

frequency (fOUTx). The user must ensure that fNCO, fVCO, fTDC, and

fPFD are within their specified frequency limits.

fTDC = fREFx/R

= fOUTx/N

(8)

fNCO = fPFD = (2 × Q/M) × fOUTx

= ((2 × Q × N)/(R × M)) × fREFx

(9)

fVCO = 2 × Q × fOUTx

= (2 × Q × N/R) × fREFx

(10)

When the reference source is auxiliary NCO 0, auxiliary NCO 1,

IUTS 0, IUTS 1, or the feedback from the other DPLL, then in

Equation 8 through Equation 10, use R = 1.

Table 77. Zero Delay Feedback Path Selection

Bits[4:0]

(Decimal)

DPLL

Internal Zero

Delay

External Zero

Delay

OUT0AP

REFA

OUT1AP

REFA

OUT0AN

REFAA

OUT1AN

REFAA

OUT0BP

REFB

OUT1BP

REFB

OUT0BN

REFBB

OUT1BN

REFBB

OUT0CP

Auxiliary REF0

Not applicable

Auxiliary REF0

OUT0CN

Auxiliary REF1

Not applicable

Auxiliary REF1

Not applicable

Auxiliary REF2

Not applicable

Auxiliary REF2

Not applicable

Auxiliary REF3

Not applicable

Auxiliary REF3

8 to 31

Not applicable

INTERNAL ZERO DELAY

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR,

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

M-DIVIDER

N DIVIDER

TDC

OUTPUT

DISTRIBUTION

DPLL

AD9546

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA

XOB

APLL

OUTxyN/

OUTxyP

REFx

OTHER DPLL

FEEDBACK TDC

DIGITAL

CROSS

POINT

MUX

REFERENCE TDCS

AUXILIARY NCOS

INVERSE USER TIME

STAMPERS (IUTS)

AUXILIARY

REFERENCE TDCS

VCO

÷2

Figure 84. Internal Zero Delay PLL Configuration

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