AD9546SLASHPCBZ datasheet(118/205 Pages) AD

118 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 118 of 205

The DPLL provides the user with two status bits to indicate

when the DPLL enters or exits hitless operation. When the

DPLL enters hitless operation, Bit 4 latches to Logic 1 in

Likewise, when the DPLL exits hitless operation, Bit 3 latches to

Logic 1 in Register 0x3011 for DPLL0 or Register 0x3016 for

DPLL1. Because these are latched status bits, to obtain visibility

of subsequent DPLL state transitions into and out of hitless

operation, the user must clear the corresponding bits in the

IRQ map (Bit 4 and Bit 3, respectively, in Register 0x200C for

DPLL0 and Register 0x2011 for DPLL1).

EXTERNAL ZERO DELAY (HITLESS) MODE

Figure 85 shows the external zero delay configuration appears

in. External zero delay mode, like internal zero delay mode, is a

hitless operating mode (see the Internal Zero Delay (Hitless)

Mode section). As such, the same status bits associated with

entering and exiting hitless operation still apply.

In external zero delay mode, the feedback path of the PLL is via an

external connection from an appropriate OUTxy output to a REFx

or an auxiliary REFx input. The user chooses the desired input

path via the same 5-bit integer used to select the feedback Q

divider in the internal zero delay configuration, but with the

decimal value applying to the External Zero Delay column in

Table 77. Typically, this feedback path is merely a direct connec-

tion, but the external path may also include an additional

frequency translation component. To discriminate between the

normal and feedback reference inputs in Figure 85, they appear

as REFx and REFy, respectively. Although Figure 85 shows REFx

and REFy, auxiliary REFx, and auxiliary REFy are equally valid.

The frequency translation factor from REFx (auxiliary REFx) to

OUTxyP/OUTxyN for external zero delay mode is

OUTx

REFx

Rx Z

where:

Ry is the divide ratio of the R divider associated with REFy.

REFy refers to any reference input (other than the REFx input).

Rx is the divide ratio of the R divider associated with REFx.

REFx refers to any reference input (other than the REFy input).

Z is the external frequency translation factor such that

Z =

REFy

OUTx

To provide true hitless operation, external zero delay mode

requires a constraint on the relationship between fREFx and fREFy.

Namely, fREFy/fREFx must be an integer greater than or equal to 1.

The NCO, VCO, TDCs, and the APLL PFD inputs each have

specific frequency limits. The following formulas relate fNCO,

fVCO, fTDC, and fPFD to Z, fREFx, fOUTx, and divider values. Note that

each formula has two solutions: one with respect to the input

frequency (fREFx) and the other with respect to the output

frequency (fOUTx). The user must ensure that fNCO, fVCO, fTDC, and

fPFD are within their specified frequency limits.

fTDC = fREFx/Rx

= (Z/Ry) × fOUTx

(11)

fNCO = fPFD = ((2 × Q × Ry)/(Rx × M × Z)) × fREFx

= (2 × Q/M) × fOUTx

(12)

fVCO = ((2 × Q × Ry)/(Rx × Z)) × fREFx

= 2 × Q × fOUTx

(13)

When the reference source is auxiliary NCO 0, auxiliary

NCO 1, or the feedback from the other DPLL, then in Equation

11 through Equation 13, use Rx = 1.

Although the feedback divider (N divider) does not appear in

Figure 85, the N divider requires special treatment for external

zero delay operation. See the DPLL Feedback Divider (N

Divider) section for details.

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR,

AND NCO

PFD

AND

LOOP

FILTER

M DIVIDER

OUTPUT

DISTRIBUTION

DPLL

AD9546

SYSTEM

CLOCK

LFx

XOA

XOB

APLL

OUTxyN/

OUTxyP

REFx

OTHER DPLL

FEEDBACK TDC

DIGITAL

CROSS

POINT

MUX

REFERENCE TDCS

AUXILIARY NCOS

INVERSE USER TIME

STAMPERS (IUTS)

REFy

AUXILIARY

REFERENCE TDCS

VCO

÷2

NOTE

1. REFx AND REFy CAN EACH BE ANY OF THE REFERENCE INPUTS, BUT NOT THE SAME REFERENCE INPUT.

Figure 85. External Zero Delay PLL Configuration

AD9546/PCBZ Scheda tecnica(PDF) 118 Page - Analog Devices

AD9546/PCBZ Scheda tecnica(HTML) 118 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL