AD9546SLASHPCBZ datasheet(116/205 Pages) AD

116 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 116 of 205

PHASE BUILDOUT MODE

Figure 83 shows the phase buildout configuration. In phase

buildout mode, when the AD9546 switches from one input

reference to another, there is virtually no phase disturbance at

the output. Because the AD9546 uses time stamps generated by

the reference TDCs, the difference between the time stamps

from the old and new reference equates to a phase difference.

Thus, the AD9546 can assess the phase offset and automatically

compensate at switchover (see the Initial Phase Skew Refinement

Steps section for more detail).

The frequency translation factor for phase buildout mode is









××





OUTx

REF x

FRAC

MOD

R Q

where:

N is the N divider integer part.

FRAC is the N divider fractional part.

MOD is the N divider fractional modulus.

M is the divide ratio of the APLL feedback divider.

R is the divide ratio of the input reference divider.

Q is the divide ratio of the distribution divider.

However, the NCO, VCO, TDCs, and the APLL PFD inputs

each have specific frequency limits. The following formulas

relate the output frequency of the NCO (fNCO), fVCO, fTDC, and

fPFD to fREFx, fOUTx, and divider values. Note that each formula has

two solutions: one with respect to the input frequency (fREFx)

and the other with respect to the output frequency (fOUTx). The

user must ensure that fNCO, fVCO, fTDC, and fPFD are within their

specified frequency bounds.

fTDC = fREFx/R

= (2 × Q/(M × (N + FRAC/MOD))) × fOUTx

(5)

where:

fREFx is the reference frequency for a specific reference input, for

example, REFA, REFAA, REFB, or REFBB.

fOUTx is the output frequency for a specific distribution output,

for example, OUT0C or OUT1A.

fNCO = fPFD = (2 × Q/M) × fOUTx

= ((N + FRAC/MOD)/R) × fREFx

(6)

fVCO = 2 × Q × fOUTx

= ((N + FRAC/MOD) × M/R) × fREFx

(7)

When the reference source is auxiliary NCO 0, auxiliary NCO 1, or

the feedback from the other DPLL, then in Equation 5 through

Equation 7, use R = 1.

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR,

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

M DIVIDER

N DIVIDER

TDC

OUTPUT

DISTRIBUTION

PHASE

BUILD

OUT

DPLL

AD9546

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA

XOB

APLL

OUTxyN/

OUTxyP

REFx

OTHER DPLL

FEEDBACK TDC

DIGITAL

CROSS

POINT

MUX

REFERENCE TDCS

AUXILIARY NCOS

INVERSE USER TIME

STAMPERS (IUTS)

AUXILIARY

REFERENCE TDCS

VCO

÷2

Figure 83. Phase Buildout PLL Configuration

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