WM8281ECSSLASHR datasheet(131/392 Pages) CIRRUS

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WM8281

Rev 4.0

131

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5176

(1438h)

3:0

DSP4_START_IN

_SEL [3:0]

DSP4 Firmware Execution control

Selects the trigger for DSP4 firmware

execution.

0 = DMA

1 = DSP1 Start 1

2 = DSP1 Start 2

3 = DSP2 Start 1

4 = DSP2 Start 2

5 = DSP3 Start 1

6 = DSP3 Start 2

11 = IRQ2

All other codes are Reserved.

Note that the DSP4_START bit will also

start the DSP4 firmware execution,

regardless of this register setting.

Table 28 DSP Firmware Execution

DSP DIRECT MEMORY ACCESS (DMA) CONTROL

Each DSP provides a multi-channel DMA function; this is configured using the registers described in

Table 29.

There are 8 WDMA (DSP input) and 6 RDMA (DSP output) channels for each DSP; these are

enabled using the DSPn_WDMA_CHANNEL_ENABLE and DSPn_RDMA_CHANNEL_ENABLE

fields. The status of each WDMA channel is indicated in DSPn_WDMA_ACTIVE_CHANNELS.

The DMA can access the X data memory or Y data memory associated with the respective DSP. The

applicable memory is selected using bit [15] of the respective *_START_ADDRESS register.

The start address of each DMA channel is configured as described in Table 29. Note that the required

address is defined relative to the base address of the selected (X data or Y data) memory.

The buffer length of the DMA channels is configured using the DSPn_WDMA_BUFFER_LENGTH

field. The selected buffer length applies to all enabled WDMA or RDMA channels.

Note that the start address registers, and WDMA buffer length registers, are defined in 24-bit DSP

data word units. This means that the LSB of these fields represents one 24-bit DSP memory word.

(Note that this differs from the WM8281 register map layout, as described in Table 26).

The parameters of a DMA channel (ie. Start Address or Offset Address) must not be changed whilst

the respective DMA is enabled. All of the DMA channels must be disabled before changing the

WDMA buffer length.

Each DMA channel uses a twin buffer mechanism to support uninterrupted data flow through the

DSP. The buffers are called ‘ping’ and ‘pong’ respectively, and are of configurable size, as noted

above. Data is transferred to/from each of the buffers in turn.

When the ‘ping’ input data buffer is full, the DSPn_PING_FULL bit will be asserted (set to ‘1’), and a

‘DSP Start’ signal will be generated. The ‘Start’ signal from the DMA is typically used to start Firmware

execution, as noted in Table 28

. Meanwhile, further DSP input data will be filling up the ‘pong’ buffer.

When the ‘pong’ input buffer is full, the DSPn_PONG_FULL bit will be asserted, and another ‘DSP

Start’ signal will be generated. The DSP Firmware must take care to read the input data from the

applicable buffer, in accordance with the DSPn_PING_FULL and DSPn_PONG_FULL status bits.

Twin buffers

are also used on the DSP output (RDMA) channels. The output ‘ping’ buffers are

emptied at the same time as the input ‘ping’ buffers are filled; the output ‘pong’ buffers are emptied at

the same time as the input ‘pong’ buffers are filled.

Further details of the DMA are provided in the software programming guide - please contact your local

Cirrus Logic representative if required.

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