WM8281ECSSLASHR datasheet(129/392 Pages) CIRRUS

129 / 392 page

WM8281

Rev 4.0

129

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DSP4_CLK_AVAI

DSP4 Clock Availability

(Read only)

0 = No Clock

1 = Clock Available

Note

– this bit exists for legacy software

support only; it is not recommended for

future designs, as the readback may be

unreliable on the latest device

architectures.

Table 27 DSP Clocking Control

DSP FIRMWARE EXECUTION

After the DSP firmware has been loaded, and the clocks configured, the DSP blocks are enabled

using the DSPn_CORE_ENA register bits. When the DSP is configured and enabled, the firmware

execution can be started by writing ‘1’ to the respective DSPn_START bit.

Alternative methods to trigger the firmware execution can also be configured using the

DSPn_START_IN_SEL register fields. Note that this provides the capability to synchronously trigger

multiple DSP blocks.

Using the DSPn_START_IN_SEL registers, the DSP firmware execution can be linked to the

respective DMA function, the IRQ2 status, or to configurable ‘DSPn Start’ signals from another DSP.

The ‘DSPn Start’ signals are generated within the DSP cores, enabling any of the DSP blocks to

trigger code execution in another DSP.

The DSPn_CORE_ENA bit must be set to ‘1’ to enable firmware execution on the respective DSP

block. Note that the usage of the DSPn_START bit may vary depending on the particular software

that is being executed: in some applications (eg. when an alternative trigger is selected using

DSPn_START_IN_SEL), writing to the DSPn_START bit will not be required.

For read/write access to the DSP firmware memory registers, the respective firmware execution must

be disabled by setting the DSPn_CORE_ENA bit to ‘0’.

The audio signal paths connecting to/from the DSP processing blocks are configured as described in

the “Digital Core” section. Note that the DSP firmware must be loaded and enabled before audio

signal paths can be enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4352

(1100h)

DSP1

Control 1

DSP1_CORE_EN

DSP1 Enable

Controls the DSP1 firmware execution

0 = Disabled

1 = Enabled

DSP1_START

DSP1 Start

Write ‘1’ to Start DSP1 firmware execution

R4408

(1138h)

3:0

DSP1_START_IN

_SEL [3:0]

DSP1 Firmware Execution control

Selects the trigger for DSP1 firmware

execution.

0 = DMA

3 = DSP2 Start 1

4 = DSP2 Start 2

5 = DSP3 Start 1

6 = DSP3 Start 2

7 = DSP4 Start 1

8 = DSP4 Start 2

11 = IRQ2

All other codes are Reserved.

Note that the DSP1_START bit will also

start the DSP1 firmware execution,

regardless of this register setting.

WM8281ECS/R Scheda tecnica(PDF) 129 Page - Cirrus Logic

WM8281ECS/R Scheda tecnica(HTML) 129 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL