AD9546SLASHPCBZ datasheet(115/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 115 of 205

TRANSLATION MODES

Overview

The translation modes govern the way the DPLL responds

when it acquires a reference signal. In general, at the start of a

reference acquisition, the feedback of the DPLL and reference

signals do not have the same phase relationship. As such, when

the DPLL begins an acquisition, it likely exhibits a significant

output disturbance as the loop attempts to compensate for the

phase mismatch. To deal with the output disturbance that

typically results from a reference acquisition, the AD9546 offers

two translation mode types: phase buildout and hitless.

A phase buildout acquisition virtually eliminates the output

disturbance that results from an initial phase mismatch. During

a phase buildout acquisition, the DPLL effectively measures the

initial phase offset between its feedback and reference inputs

and inserts the measured phase offset into the feedback path of

the loop. The measured phase offset is the phase buildout offset.

Insertion of the phase buildout offset into the loop effectively

eliminates the initial phase difference between the feedback and

reference signals, thereby minimizing the disturbance at the

output of the DPLL. The insertion of the phase buildout offset

implies a phase difference between the output of the DPLL and

reference clock signals. This phase difference is the expected

behavior for a phase buildout reference acquisition.

Note that during a phase buildout acquisition, the phase slew

rate limit function does not operate on the buildout phase

transition (see the Phase Slew Rate Limit section of the Digital

PLL (DPLL) section for details on the phase slew rate limiter).

Unlike a phase buildout acquisition, a hitless acquisition

ultimately results in a phase match of the output of the DPLL

and reference clock signals. As such, a hitless translation mode

is a prerequisite for zero delay operation. Given a phase

mismatch between the reference of the DPLL and feedback

signals at the start of an acquisition, the DPLL temporarily

changes its output frequency to steer the phase difference

toward zero. The AD9546 optimizes this process by assessing

the initial phase relationship between the reference and

feedback signals and steering toward the reference clock edge

exhibiting the smallest relative phase offset.

Because a hitless acquisition undergoes frequency changes to

bring about phase alignment, there can be a significant phase

disturbance at the output while the loop locks to the phase of

the reference (even if the initial feedback and reference frequencies

are identical). The user can minimize this disturbance by placing a

limit on the DPLL output frequency excursion (caused by a

phase rate of change (δθ/δt) at its input) via the phase slew limit

feature (see the Phase Slew Rate Limit section). Furthermore,

the user can place a limit on the overall output frequency

excursion (due to both an input frequency offset and δθ/δt) by

using the frequency clamp feature (see the Tuning Word Offset

Clamp section).

Even during a hitless acquisition, the AD9546 builds out the

initial phase offset between the reference and feedback signals

(as though the device is performing a phase buildout

acquisition) to help mitigate the disturbance at the output.

However, unlike the case of a phase buildout acquisition, the

phase slew rate limiter is operational during a hitless

acquisition (see the Phase Slew Rate Limit section for details on

the phase slew rate limiter) and applies slew rate limiting to the

buildout phase transition as needed.

For further information on how a PLL responds to switching

from one reference to another under hitless and phase buildout

operating modes, see the AN-1420 Application Note.

Translation Mode Selection

PLL0 and PLL1 can operate in any one of three modes:

•

Phase buildout mode

•

Internal zero delay mode (hitless)

•

External zero delay mode (hitless)

The zero delay modes constitute hitless rather than phase

buildout operation. For details on each mode, see the Phase

Buildout Mode section, Internal Zero Delay (Hitless) Mode

section, and External Zero Delay (Hitless) Mode section.

The user selects the operating mode via the translation profile

registers. That is, each profile gives the user the option of selecting

any one of the three operating modes for that specific profile. To

select the operating mode, use Bits[1:0] in the register at the

start address of the translation profile in Table 74 plus an offset

of 3 (decimal). Bits[1:0] select the operating mode per Table 76.

Table 76. Frequency Translation Modes

Bits[1:0] (Decimal)

Translation Mode

Phase buildout

Internal zero delay

Not applicable

External zero delay

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