AD9546SLASHPCBZ datasheet(113/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 113 of 205

FREQUENCY TRANSLATION LOOPS

FREQUENCY TRANSLATION LOOPS OVERVIEW

The frequency translation capability of the AD9546 comprises

two independent dual-PLL channels (Channel 0 and Channel 1).

Each PLL channel comprises a DPLL followed by an APLL.

Both channels have programmable reference dividers at the

input and programmable channel dividers at the output. Figure 82

shows a block diagram of a single channel. REFx and REFy can

each be any of the reference inputs, but not the same reference

input.

The DPLL channels (DPLL0 and DPLL1) are capable of low

loop bandwidths (µHz) well suited for jitter cleanup

applications involving the 1 pulse per second (pps) input

signals that originate from global positioning system (GPS) and

global navigation satellite system (GNSS) receivers. The DPLL

is of the fractional-N variety but is capable of Integer N

operation when the fractional part is set to zero.

The DPLL provides an output frequency of up to approximately

400 MHz. The DPLL also plays a role in the automatic

reference switching capability of the AD9546 and its ability to

provide hitless and phase buildout functionality.

The APLL is of the Integer N variety with an integrated VCO

and provides the high frequency upconversion capability of the

cascaded DPLL/APLL pair. Unlike the two DPLLs, which are

identical, the two APLLs differ slightly. Specifically, they have

nonoverlapping VCO ranges with APLL0 spanning 2.424 GHz

to 3.232 GHz and APLL1 spanning 3.232 GHz to 4.040 GHz.

TRANSLATION PROFILES

DPLL0 and DPLL1 each have six dedicated sections in the

Profile 0.0 through Translation Profile 0.5 for DPLL0 and

Translation Profile 1.0 through Translation Profile 1.5 for

DPLL1). Each translation profile consists of the following

programmable parameters:

•

Profile enable

•

Profile priority

•

Translation mode selection

•

Input reference source selection

•

N divider value (integer, fraction, and modulus)

•

DPLL loop filter bandwidth

•

Reference and feedback TDC tagging options

•

DPLL fast acquisition options

Table 74 shows the translation profile address ranges.

Table 74. Translation Profile Register Address Ranges

Translation Profile

Start Address

End Address

0.0

0x1200

0x1217

0.1

0x1220

0x1237

0.2

0x1240

0x1257

0.3

0x1260

0x1277

0.4

0x1280

0x1297

0.5

0x12A0

0x12B7

1.0

0x1600

0x1617

1.1

0x1620

0x1637

1.2

0x1640

0x1657

1.3

0x1660

0x1677

1.4

0x1680

0x1697

1.5

0x16A0

0x16B7

When a given profile is in effect, the DPLL uses the parameters

as specified in that profile. That is, the DPLL has no memory of

the given profile when switching to another profile.

INTERNAL ZERO DELAY

EXTERNAL ZERO DELAY (MAY INCLUDE ADDITIONAL FREQUENCY TRANSLATION)

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

M DIVIDER

N DIVIDER

TDC

OUTPUT

DISTRIBUTION

PHASE

BUILD

OUT

DPLL

AD9546

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA

XOB

APLL

OUTxyN/

OUTxyP

REFx

OTHER DPLL

FEEDBACK TDC

DIGITAL

CROSS

POINT

MUX

REFERENCE TDCS

AUXILIARY NCOS

INVERSE USER TIME

STAMPERS (IUTS)

REFy

AUXILIARY

REFERENCE TDCS

VCO

÷2

NOTE

1. REFx AND REFy CAN EACH BE ANY OF THE REFERENCE INPUTS, BUT NOT THE SAME REFERENCE INPUT.

Figure 82. Frequency Translation Loop Block Diagram

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