AD9546SLASHPCBZ datasheet(112/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 112 of 205

AA, B, or BB) results in disturbing all the Output 1 clock

outputs. These output clock disturbances result from the

synchronization process. However, the disturbances are glitch

free, because the synchronization sequence mutes the affected

output drivers during synchronization.

The aforementioned output clock disturbances are avoidable,

however, when the clock source to the Q dividers is the system

clock (see Table 62) and the system clock synchronization mask

bits are Logic 1 (see the Q Divider Clock Source Selection

section) for a subset of the device outputs.

AUTOSYNCHRONIZATION TRIGGER

Although the AD9546 provides the user with the ability to

synchronize the distribution outputs via a manual synchroniza-

tion trigger, it is not a recommended action. Instead, the

AD9546 provides an autosynchronization trigger feature that

applies only after meeting certain conditions, which overcomes

potential usability issues associated with manual trigger scenarios.

The immediate autosynchronization mode (see Table 73) is an

effective replacement for manual synchronization triggering.

The user selects the desired autosynchronization trigger

conditions via Bits[1:0] of Register 0x10DB for PLL0 and

autosynchronization conditions.

Table 73. Autosynchronization Mode Selections

Bits[1:0] (Decimal)

Autosynchronization Mode

Disabled (default)

Immediate

On DPLL phase lock

On DPLL frequency lock

Autosynchronization enables the AD9546 to execute a

distribution synchronization sequence without any user

intervention. The nonzero autosynchronization selections

specify conditions for generating an autosynchronization

trigger.

When autosynchronization mode = 0 (default), only manual or

autoreconfiguration triggers are possible. When autosynchroniza-

tion mode ≠ 0, the autosynchronization trigger feature is in

effect.

When autosynchronization is active (autosynchronization

mode ≠ 0), nothing happens until the system clock PLL

indicates a locked status. The autosynchronization mechanism

then enters an autosynchronization trigger detection loop

awaiting the specified autosynchronization event. When

autosynchronization mode = 1, the autosynchronization event

constitutes the indication of a locked status by the system clock

PLL. When autosynchronization mode = 2, the

autosynchronization event constitutes an indication of phase

lock by the DPLL.

When autosynchronization mode = 3, the autosynchronization

event constitutes an indication of frequency lock.

After the autosynchronization trigger occurs for a PLL channel,

the autosynchronization trigger generation sequence terminates.

Subsequent autosynchronization sequences on the same PLL

channel are not possible unless the user programs Bit 0 = 1 of

REFERENCE SYNCHRONIZATION

Output clock synchronization establishes a coincident starting

time among output clocks (usually on a per PLL channel basis).

Output clock synchronization, however, is generally

asynchronous with respect to input reference clock signal

edges. The reference synchronization feature allows the user to

make a rising edge of the input reference clock an additional

gating item for synchronization of the output clocks. Reference

synchronization establishes a small fixed phase relationship

(~30 ns) between the input and output clocks (assuming the

output clock frequency is an integer multiple of the input

reference frequency). Establishing an initial fixed phase

relationship between the input and output clocks minimizes the

DPLL acquisition time by making it deterministic rather than

completely random.

The reference synchronization feature requires a hitless profile

be active when reference synchronization is in effect. The

reference synchronization feature does not function with a

phase buildout profile.

Like most of the other synchronization features, reference

synchronization applies on a per PLL channel basis. To enable

the reference synchronization feature, use Bit 2 (reference

synchronization) of Register 0x10DB for PLL0 and Register

0x14DB for PLL1. Setting the reference synchronization bit,

which is Logic 0 by default, enables reference synchronization

of those outputs associated with the corresponding PLL

channel.

When using reference synchronization in conjunction with

autosynchronization mode (that is, autosynchronization mode

= 1, 2, or 3), be sure to program the reference synchronization

bit to Logic 1 and assert the I/O update bit prior to

programming autosynchronization mode = 1, 2, or 3.

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