HC05V7GRSSLASHD datasheet(22/170 Pages) NXP

22 / 170 page

SECTION 1: GENERAL DESCRIPTION

Page 8

MC68HC05V7 Specification Rev. 1.0

1.4

MCU STRUCTURE

The overall block diagram of the MC68HC05V7 is shown in Figure 1-6.

Figure 1-6:

MC68HC05V7 Block Diagram

STK PTR

WATCHDOG

OSCILLATOR

COND CODE REG 1 1 1

I N Z C

INDEX REG

CPU CONTROL

0 0 0

RESET

OSC 1

OSC 2

SRAM -384 BYTES

USER ROM -10K BYTES

IRQ

ALU

68HC05 CPU

ACCUM

PROGRAM COUNTER

CPU REGISTERS

÷2

PA7 *

PA0 *

PA1 *

PA2 *

PA3 *

PA4 *

PA5 *

PA6 *

VSSD

* IRQ Interrupt Capability

EEPROM -128 BYTES

16-BIT TIMER with

1 IPC & 1 OPC

PB7/TCAP

PB0

PB1

PB2

PB3

PB4

PB5

PB6/TCMP

PC7 *

PC0 *

PC1 *

PC2 *

PC3 *

PC4 *

PC5 *

PC6 *

MCU POWER SUPPLY

REGULATION

VDD

LVR

VBATT

1 Channel

38 frequency, 6-bit PWM

Internal

VDD

SPI

PF3/MISO

PF2/MOSI

PF1/SCLK

PWM

VSSD

AD0/PD0

AD1/PD1

AD2/PD2

AD3/PD3

AD4/PD4

AD5/PD5

AD6/PD6

AD7/PD7

AD8/PE0

AD9/PE1

AD10/PE2

AD11/PE3

AD12/PE4

AD13/PE5

AD14/PE6

AD15/PE7

VREFH

VREFL

MDLC

LOAD

BUS

REXT2

REXT1

VSSA2

E not bonded out

6-pin SDIP

PF0/SS

Interrupt

VSSA1

VCCA

To A/D

VCC

VIGN

CLKIN

8-BIT TIMER with RTI

VDD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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