HC05V7GRSSLASHD datasheet(63/170 Pages) NXP

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SECTION 7: POWER SUPPLY AND REGULATION

Page 49

MC68HC05V7 Specification Rev. 1.0

7.4

REGULATOR CONTROL LOGIC

The ignition state monitor pin, VIGN, or the MDLC BUS pin (provided the MDLCPU mask

option is selected) allows the user to wake-up the primary power supply and subsequently

the MCU. A positive transition applied to either pin will enable the primary regulator. The

state of the VIGN pin can be determined by reading the IGNS bit of the MISCELLANEOUS

MISCELLANEOUS register. The BUS or VIGN pin need not be low to write the PDC bit.

Once the regulator has been disabled, a rising edge on VIGN or BUS will re-enable the

regulator.

To ensure the validity of the PDC bit during a VDD transition, the PDC bit is always copied

into a latch powered by the secondary regulator. The bit is copied during a write to the

MISCELLANEOUS register. When the regulator is powered up by a rising edge of BUS or

VIGN, the latch that contains the copy of the PDC bit will be initialized to a 1 and may have

a different value than the PDC bit itself. Software should always initialize the PDC bit to a

1. The latch will be set on the rising edge of VIGN or BUS. This will give the primary

regulator, CPU, and software ample time to start up and initialize the PDC bit to a 1. At this

point, the MCU will transition to the Power Up Mode. (See Figure 7-2.)

In order to ensure that the primary regulator starts up when VBATT voltage is applied to the

MCU, a low to high transition should be provided on the VIGN pin once VBATT reaches

minimum level, shown in Figure 7-3.

Figure 7-3: Regulator Startup

NOTE:

Once enabled, the regulator can only be disabled through software.

Voltage

time

Min

VBATT

<= 0.4*VBATT

VBATT

VIGN

>min VBATT

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