HC05V7GRSSLASHD datasheet(7/170 Pages) NXP

7 / 170 page

Page vii

MC68HC05V7 Specification Rev. 1.0

15.2.4

MDLC TX CONTROL REGISTER (MTCR) $10................100

15.2.5

MDLC RX STATUS REGISTER (MRSR) $11...................101

15.3

MDLC Rx/Tx BUFFERS .........................................................103

15.3.1

OUTLINE...........................................................................103

15.3.2

RX BUFFERS....................................................................105

15.3.3

TX BUFFER ......................................................................106

15.4

MDLC PROTOCOL HANDLER ..............................................108

15.4.1

OUTLINE...........................................................................108

15.4.2

Rx & Tx SHIFT REGISTERS ............................................108

15.4.3

STATE MACHINE .............................................................109

15.5

MDLC MUX INTERFACE .......................................................112

15.5.1

Rx DIGITAL FILTER..........................................................112

15.5.2

J1850 FRAME FORMAT...................................................114

15.5.3

J1850 VPW SYMBOLS .....................................................116

15.5.4

J1850 VPW VALID/INVALID BITS & SYMBOLS ..............117

15.5.5

MESSAGE ARBITRATION ...............................................121

15.6

MDLC PHYSICAL INTERFACE .............................................123

15.6.1

OUTLINE...........................................................................123

15.6.2

MUX INTERFACE SIGNALS ............................................126

15.6.3

PINS ..................................................................................127

15.7

MDLC APPLICATION NOTES ...............................................128

15.7.1

INITIALIZATION ................................................................128

15.7.2

TRANSMITTING A MESSAGE .........................................128

15.7.3

RECEIVING A MESSAGE ................................................128

15.7.4

RECEIVING A MESSAGE IN BLOCK MODE...................129

15.7.5

MDLC STOP MODE..........................................................130

15.7.6

MDLC WAIT MODE ..........................................................130

15.7.7

CONTROLLING EXTERNAL VOLTAGE

REGULATORS................................................................130

SECTION 16

INSTRUCTION SET .................................................... 133

16.1

16.2

READ-MODIFY-WRITE INSTRUCTIONS..............................133

16.3

BRANCH INSTRUCTIONS.....................................................134

16.4

BIT MANIPULATION INSTRUCTIONS...................................134

16.5

CONTROL INSTRUCTIONS ..................................................135

16.6

ADDRESSING MODES..........................................................135

16.6.1

IMMEDIATE ......................................................................136

16.6.2

DIRECT .............................................................................136

16.6.3

EXTENDED.......................................................................136

16.6.4

RELATIVE .........................................................................136

16.6.5

INDEXED, NO OFFSET....................................................136

16.6.6

INDEXED, 8-BIT OFFSET ................................................136

16.6.7

INDEXED, 16-BIT OFFSET ..............................................137

16.6.8

BIT SET/CLEAR................................................................137

16.6.9

BIT TEST AND BRANCH..................................................137

16.6.10

INHERENT ........................................................................137

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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