HC05V7GRSSLASHD datasheet(47/170 Pages) NXP

47 / 170 page

SECTION 5: INTERRUPTS

Page 33

MC68HC05V7 Specification Rev. 1.0

Figure 5-2:

IRQ Function Block Diagram

The IRQ pin is one source of an external interrupt. All Port A pins (PA0 thru PA7) and/or all

Port C pins (PC0 thru PC7) act as other external interrupt sources. These sources each

have their own interrupt latch but are all combined into a single external interrupt request.

The Port A and Port C interrupt sources are negative (falling) edge sensitive only. Note

that all Port A pins and all Port C pins are ANDed together, if conﬁgured as an input, to form

the negative edge signal which sets the corresponding ﬂag bits. A high to low transition on

any Port A or Port C pin conﬁgured as an input will therefore set the respective ﬂag bit. If a

Port A or Port C pin is an input and is not used as a switch input in the system, it must

remain high to prevent spurious interrupts from occurring. Refer to 9.1.3 PORT A/C I/O PIN

INTERRUPTS for more detail on Port A/Port C interrupts. The IRQ pin interrupt source may

be selected to be either edge sensitive or edge and level sensitive through a mask option

or an MOR bit. If the EDGE sensitive interrupt option is selected for the IRQ pin, only the

IRQ

LATCH

IRQ Pin

IRQE

LEVEL

(MASK option)

IRQF

to IRQ

processing

in CPU

IRQA

to BIH & BIL

instruction

sensing

RST

PA0

PA7

IRQPA

LATCH

IRQPAE

IRQPCE

IRQPAF

IRQPCF

IRQ Vector Fetch

IRQPC

LATCH

DDRA0

DDRA7

PC0

PC7

DDRC0

DDRC7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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