HC05V7GRSSLASHD datasheet(78/170 Pages) NXP

78 / 170 page

SECTION 9: PARALLEL I/O

Page 64

MC68HC05V7 Specification Rev. 1.0

Figure 9-3:

Port D and Port E Circuitry

9.4

PORT F

Port F is a 4-bit bidirectional port which shares all of its pins with the SPI subsystem. If the

SPI is enabled, Port F3-1 are disabled as regular I/O pins. PF0 can still function as an

output if the DDR bit is set. Each Port F pin is controlled by the corresponding bits in a data

direction register and a data register. The Port F Data Register is located at address $002C.

The Port F Data Direction Register (DDRF) is located at address $002E. Reset clears the

DDRF register. The Port F Data Register is unaffected by reset. Port F is shared with the

SPI.

9.4.1

PORT F DATA REGISTER

Each Port F I/O pin has a corresponding bit in the Port F Data Register. When a Port F pin

is programmed as an output the state of the corresponding data register bit determines the

state of the output pin. When a Port F pin is programmed as an input, any read of the Port

F Data Register will return the logic state of the corresponding I/O pin. The Port F data

unaffected by reset.

9.4.2

PORT F DATA DIRECTION REGISTER

Each Port F I/O pin may be programmed as an input by clearing the corresponding bit in

the DDRF, or programmed as an output by setting the corresponding bit in the DDRF. The

DDRF can be accessed at address $002E. If the SPI subsystem is enabled (SPE bit is set),

the DDRF bit corresponding to PF0 will determine the function of the PF0 pin. If DDRF0 is

cleared, the PF0 pin functions as a SS (slave select) input to the SPI. If DDRF0 is set, then

PF0 can serve as a normal output pin. When the SPI subsystem is enabled, the DDRF3-1

bits are set or cleared according to the required pin function. The DDRF is cleared by reset.

Read $0003/2B

Input

Internal HC05

Data Bus

VSS

To A/D Sampling Circuitry

To A/D Channel Select Logic

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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