HC05V7GRSSLASHD datasheet(41/170 Pages) NXP

41 / 170 page

SECTION 4: CPU CORE

Page 27

MC68HC05V7 Specification Rev. 1.0

4.1.5.2

Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts

are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt

mask is automatically set after the CPU registers are saved on the stack, but before the

interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the

interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt

mask is cleared.

A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the

interrupt mask to its state before the interrupt was encountered. After any reset, the

interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), STOP, or WAIT

instructions.

4.1.5.3

Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical operation, or

data manipulation was negative. (Bit 7 of the result was a logical one.)

The negative bit can also be used to check an often-tested flag by assigning the flag to bit

7 of a register or memory location. Loading the accumulator with the contents of that

4.1.5.4

Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical operation, data

manipulation, or data load operation was zero.

4.1.5.5

Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the

last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is

also set or cleared during bit test and branch instructions and during shifts and rotates. This

bit is not set by an INC or DEC instruction.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 41 Page - NXP Semiconductors