HC05V7GRSSLASHD datasheet(3/170 Pages) NXP

3 / 170 page

Page iii

MC68HC05V7 Specification Rev. 1.0

TABLE OF CONTENTS

SECTION 1

GENERAL DESCRIPTION .............................................. 1

1.1

FEATURES.................................................................................1

1.2

MASK OPTIONS ........................................................................2

1.3

PIN ASSIGNMENTS...................................................................2

1.4

MCU STRUCTURE ....................................................................8

1.5

FUNCTIONAL PIN DESCRIPTION ............................................9

1.5.1

VBATT.....................................................................................9

1.5.2

VDD AND VSS ........................................................................9

1.5.3

VSSA1.....................................................................................9

1.5.4

VSSA2.....................................................................................9

1.5.5

VCCA ......................................................................................9

1.5.6

VREFH AND VREFL.................................................................9

1.5.7

OSC1, OSC2.......................................................................10

1.5.8

RESET ................................................................................11

1.5.9

IRQ (MASKABLE INTERRUPT REQUEST) .......................11

1.5.10

PA0-PA7..............................................................................11

1.5.11

PB0-PB5, PB6/TCMP, PB7/TCAP ......................................11

1.5.12

PC0-PC7 .............................................................................11

1.5.13

AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7 ........................12

1.5.14

PWM....................................................................................12

1.5.15

PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO .........................12

1.5.16

BUS, LOAD, REXT1, REXT2 ..............................................12

1.5.17

VIGN.....................................................................................12

SECTION 2

MEMORY MAP .............................................................. 13

2.1

SINGLE-CHIP MODE MEMORY MAP .....................................13

2.2

I/O AND CONTROL REGISTERS ............................................13

2.3

RAM..........................................................................................14

2.4

ROM .........................................................................................15

2.5

EEPROM ..................................................................................15

SECTION 3

EEPROM ........................................................................ 21

3.1

EEPROM PROGRAMMING REGISTER $1C ..........................21

3.1.1

CPEN - Charge Pump Enable.............................................21

3.1.2

ER1:ER0 - Erase Select Bits...............................................21

3.1.3

LATCH.................................................................................22

3.1.4

EERC - EEPROM RC Oscillator Control.............................22

3.1.5

EEPGM - EEPROM Programming Power Enable...............22

3.2

OPERATION IN STOP AND WAIT...........................................24

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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