HC05V7GRSSLASHD datasheet(99/170 Pages) NXP

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SECTION 14: SERIAL PERIPHERAL INTERFACE

Page 85

MC68HC05V7 Specification Rev. 1.0

14.1.4

Slave Select (SS/PF0)

The slave select (SS) input line is used to select a slave device. It has to be low prior to

data transactions and must stay low for the duration of the transaction.The SS line on the

master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the SPSR.

When CPHA=0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS

must go high between successive characters in an SPI message. When CPHA=1, SS may

be left low for several SPI characters. In cases where there is only one SPI slave MCU, its

SS line could be tied to VSS as long as CPHA=1 clock modes are used. The SS pin is

shared with the PF0 pin. See 9.4PORT F for additional information on the SS pin.

14.2

FUNCTIONAL DESCRIPTION

Figure 14-2 shows a block diagram of the serial peripheral interface circuitry. When a

master device transmits data to a slave via the MOSI line, the slave device responds by

sending data to the master device via the master’s MISO line. This implies full duplex

transmission with both data out and data in synchronized with the same clock signal. Thus,

the byte transmitted is replaced by the byte received and eliminates the need for separate

transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that

the I/O operation has been completed.

The SPI is double buffered on read, but not on write. If a write is performed during data

transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This

condition will cause the write collision (WCOL) status bit in the SPSR to be set. After a data

byte is shifted, the SPIF flag of the SPSR is set.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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