HC05V7GRSSLASHD datasheet(91/170 Pages) NXP

91 / 170 page

SECTION 12: CORE TIMER

Page 77

MC68HC05V7 Specification Rev. 1.0

12.1.6

RTFC - Real Time Interrupt Flag Clear

When a “1” is written to this bit, RTIF is cleared. Writing a “0” has no effect on the RTIF bit.

This bit always reads as zero.

12.1.7

RT1:RT0 - Real Time Interrupt Rate Select

These two bits select one of four taps from the Real Time Interrupt circuit. Table 12-1 shows

the available interrupt rates with a 2.1 and 1.05MHz bus clock. Reset sets these two bits

which selects the lowest periodic rate and gives the maximum time in which to alter these

bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period

is imminent or uncertain. If the selected tap is modified during a cycle in which the counter

is switching, an RTIF could be missed or an additional one could be generated. To avoid

problems, the COP should be cleared before changing RTI taps.

Table 12-1: RTI and COP Rates at 2.1 MHz

12.2

COMPUTER OPERATING PROPERLY (COP) RESET

The COP watchdog timer function is implemented on this device by using the output of the

RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table

12-1. If the COP circuit times out, an internal reset is generated and the normal reset vector

is fetched. Preventing a COP time-out, or clearing the COP, is accomplished by writing a

“0” to bit 0 of address $3FF0. When the COP is cleared, only the final divide by eight stage

(output of the RTI) is cleared.

If the COP watchdog timer is allowed to time-out, an internal reset is generated to reset the

MCU. In addition the RESET pin will be pulled low for a minimum of 3 E Clock cycle for

emulation purposes. During a chip reset (regardless of the source), the entire Core Timer

counter chain is cleared.

The COP will remain enabled after execution of the WAIT instruction and all associated

operations apply. If the STOP instruction is disabled, execution of STOP instruction will

cause an internal reset.

This COP’s objective is to make it impossible for this part to become “stuck” or “locked-up”

and to be sure the COP is able to “rescue” the part from any situation where it might entrap

itself in an abnormal or unintended behavior. This function is a mask option.

RT1:RT0

MIN. COP RATES

214/E

RTI RATE

211/E

212/E

213/E

15.60 ms

1.95 ms

3.90 ms

7.80 ms

0.97 ms

1.95 ms

3.90 ms

109.23ms

13.65ms

27.31ms

54.61ms

54.61 ms

6.83 ms

13.65 ms

27.31 ms

(217-214)/E

(214-211)/E

(215-212)/E

(216-213)/E

1.05 MHz

2.1 MHz

1.05 MHz

2.1 MHz

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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