HC05V7GRSSLASHD datasheet(49/170 Pages) NXP

49 / 170 page

SECTION 5: INTERRUPTS

Page 35

MC68HC05V7 Specification Rev. 1.0

Figure 5-3:

IRQ Status & Control Register

5.5.1.1

IRQA - IRQ Interrupt Acknowledge

The IRQA acknowledge bit clears an IRQ interrupt by clearing the IRQ, IRQPA and IRQPC

latches. This is achieved by writing a logic one to the IRQA acknowledge bit. Writing a logic

zero to the IRQA acknowledge bit will have no effect on the any of the IRQ latches. If either

the IRQ, IRQPA or IRQPC latch is not cleared within the IRQ service routine the CPU will

re-enter the IRQ interrupt sequence continuously until the IRQ latches are all cleared. The

IRQA is useful for cancelling unwanted or spurious interrupts which may have occurred

while servicing the initial IRQ interrupt. The IRQA acknowledge bit will always read as a

logic zero. The IRQA function is activated by reset.

NOTE:

The IRQ latch is cleared automatically during the IRQ vector fetch. The

IRQPA and IRQPC latches are not cleared automatically (to permit

interrupt source differentiation) and must be cleared from within the IRQ

service routine.

5.5.1.2

IRQPCF - Port C IRQ Interrupt Request

The IRQPCF flag bit indicates that a Port C IRQ request is pending. Writing to the IRQPCF

flag bit will have no effect on it. The IRQPCF flag bit must be cleared by writing a logic one

to the IRQA acknowledge bit. In this way an additional IRQPCF flag bit that is set while in

the service routine can be ignored by clearing the IRQPCF flag bit before exiting the service

routine. If the additional IRQPCF flag bit is not cleared in the IRQ service routine and the

IRQPCE enable bit remains set, the CPU will re-enter the IRQ interrupt sequence

continuously until either the IRQPCF flag bit or the IRQPCE enable bit is clear. This bit is

operational regardless of the state of the IRQPCE bit. The IRQPCF bit is cleared by reset.

5.5.1.3

IRQPAF - Port A IRQ Interrupt Request

The IRQPAF flag bit indicates that a Port A IRQ request is pending. Writing to the IRQPAF

flag bit will have no effect on it. The IRQPAF flag bit must be cleared by writing a logic one

to the IRQA acknowledge bit. In this way an additional IRQPAF flag bit that is set while in

the service routine can be ignored by clearing the IRQPAF flag bit before exiting the service

routine. If the additional IRQPAF flag bit is not cleared in the IRQ service routine and the

IRQPAE enable bit remains set, the CPU will re-enter the IRQ interrupt sequence

continuously until either the IRQPAF flag bit or the IRQPAE enable bit is clear. This bit is

operational regardless of the state of the IRQPAE bit. The IRQPAF bit is cleared by reset.

ICSR

$001F

0000000

reset

⇒

6543210

IRQE

IRQF

IRQA

IRQPAF

IRQPAE

IRQPCE

IRQPCF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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