HC05V7GRSSLASHD datasheet(96/170 Pages) NXP

96 / 170 page

SECTION 13: PULSE WIDTH MODULATOR

Page 82

MC68HC05V7 Specification Rev. 1.0

and PSB values. For instance a PWM output of E/512 can be obtained with either

PSA1:PSA0 = 10 and PSB3-PSB0 = 0001 or PSA1:PSA0 = 01 and PSB3-PSB0 = 1000.

This scheme allows for 38 unique frequency selections.

13.2.2

PWM DATA REGISTERS

The PWM system has one 8-bit data register which hold the duty cycle for each PWM

output in the least significant 6 bits. The data bits in this register are unaffected by RESET.

Figure 13-6:

PWM Data Register

POL - PWM Polarity

1 = PWM pulse is active high.

0 = PWM pulse is active low.

13.3

PWM DURING WAIT MODE

The PWM continues normal operation during WAIT mode. To decrease power

consumption during WAIT, it is recommended that the rate select bits in the PWM Control

13.4

PWM DURING STOP MODE

In STOP mode the oscillator is stopped causing the PWM to cease functioning. Any signal

in process is aborted in whatever phase the signal happens to be in.

13.5

PWM DURING RESET

Upon RESET the PSA0 and PSA1 bits in PWM CONTROL are cleared. This disables the

PWM system and sets the PWMA output low. The user should write to the data registers

prior to enabling the PWM system (for example, prior to setting PSA1 or PSA0). This will

avoid an erroneous duty cycle from being driven.

0000-1111

fosc/16

fosc/16-fosc/

256

fosc/1024-

fosc/16384

Table 13-1:

PWM Clock Rate

PSA1:PSA0

PSB3-PSB0

RCLK

SCLK

PWM OUT

——————

—

RESET:

POL

$30

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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