HC05V7GRSSLASHD datasheet(86/170 Pages) NXP

86 / 170 page

SECTION 11: 16-BIT TIMER

Page 72

MC68HC05V7 Specification Rev. 1.0

11.4

TIMER CONTROL REGISTER (TCR) - $12

The TCR is a read/write register containing six control bits. Three bits control interrupts

associated with the timer status register flags ICF, OCF and TOF.

Figure 11-2:

Timer Control Register - $12

11.4.1

ICIE - Input Capture Interrupt Enable

1 - Interrupt enabled

0 - Interrupt disabled

11.4.2

OCIE - Output Compare Interrupt Enable

1 - Interrupt enabled

0 - Interrupt disabled

11.4.3

TOIE - Timer Overflow Interrupt Enable

1 - Interrupt enabled

0 - Interrupt disabled

11.4.4

TON - Timer On

When disabled, the timer is initialized to the reset condition.

1 - Timer enabled

0 - Timer disabled

11.4.5

IEDG - Input Edge

Value of input edge determines which level transition on TCAP pin will trigger free-

running counter transfer to the input capture register. Reset clears this bit.

1 - Positive edge

0 - Negative edge

11.4.6

OLVL - Output Level

Value of output level is clocked into output level register by the next successful

output compare and will appear on the TCMP pin.

1 - High output

0 - Low output

11.5

TIMER STATUS REGISTER (TSR) - $13

The TSR is a read-only register containing three status flag bits.

Figure 11-3:

Timer Status Register - $13

ICIE

OCIE

TOIE

TON

IEDG

OLVL

RESET

$12

ICF

OCF

TOF

00000

RESET

$13

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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