HC05V7GRSSLASHD datasheet(80/170 Pages) NXP

80 / 170 page

SECTION 10: A/D CONVERTER

Page 66

MC68HC05V7 Specification Rev. 1.0

10.3.2

INTERNAL VS. MASTER OSCILLATOR

If the MCU bus (E clock) frequency is less than 1.0 MHz, an internal RC oscillator

(nominally 1.5 MHz) must be used for the A/D conversion clock. This selection is made by

setting the ADRC bit in the A/D Status and Control Registers to 1. In STOP mode, the

internal RC oscillator is turned off automatically, though the A/D subsystem remains

enabled (ADON remains set). In WAIT mode the A/D subsystem remains functional. See

10.6 A/D DURING WAIT MODE.

When the internal RC oscillator is being used as the conversion clock, three limitations

apply:

1. The Conversion Complete Flag (COCO) must be used to determine when

a conversion sequence has been completed, due to the frequency

tolerance of the RC oscillator and its asynchronism with regard to the

MCU E clock.

2. The conversion process runs at the nominal 1.5 MHz rate but the

conversion results must be transferred to the MCU result registers

synchronously with the MCU E clock so conversion time is limited to a

maximum of one channel per E cycle.

3. If the system clock is running faster than the RC oscillator, the RC

oscillator should be turned off, and the system clock used as the

conversion clock.

10.3.3

MULTI-CHANNEL OPERATION

A multiplexer allows the A/D converter to select one of sixteen external analog signals and

four internal reference sources.

10.4

A/D STATUS AND CONTROL REGISTER (ADSCR)

The following paragraphs describe the function of the A/D Status and Control Register.

Figure 10-1:

A/D Status and Control Register

10.4.1

COCO - Conversions Complete

This read-only status bit is set when a conversion is completed, indicating that the A/D Data

Control Register, conversions of the selected channel will continue every 32 cycles until the

A/D Status and Control Register is written again. In this continuous conversion mode the

A/D Data Register will be filled with new data, and the COCO bit set, every 32 cycles. Data

from the previous conversion will be overwritten regardless of the state of the COCO bit

prior to writing.

000000

RESET:

COCO

ADON

CH4

CH3

CH2

CH1

CH0

ADRC

$1E

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 80 Page - NXP Semiconductors

HC05V7GRS/D Scheda tecnica(HTML) 80 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL