HC05V7GRSSLASHD datasheet(68/170 Pages) NXP

68 / 170 page

SECTION 7: POWER SUPPLY AND REGULATION

Page 54

MC68HC05V7 Specification Rev. 1.0

Figure 7-7: HC705V8 Internal Power Routing

1) VDD to VSSD (pins 30 & 31): On-chip regulator output decoupling. As with any reg-

ulator, the output must be adequately decoupled to maintain stability of the regulator.

Decouple with at least 10 uF tantalum or aluminum electrolytic bulk in parallel with 0.1uF

ceramic or polystyrene capacitor for high frequency (HF) stability. Locate both capacitors

as close as possible to the VDD and VSSD pins, ensuring the HF capacitor is closest. The

two VSSD pins should be externally connected together.

PF3/MISO

PF2/MOSI

PF1/SCLK

PF0/SS

PB0

PB1

PB2

PB3

PB4

PB5

PB6/TCMP

PB7/TCAP

VSSA2

LOAD

BUS

VPP

N.C.

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PE7/AN

PE6/AN

PE5/AN

PE4/AN

PD7/AN

PD6/AN

PD5/AN

PD4/AN

PD3/AN

Regulator

DLC

A/D

R ~ 40 ohns

Digital Logic

Blocks

68-pin PLCC package shown

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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