HC05V7GRSSLASHD datasheet(26/170 Pages) NXP

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SECTION 1: GENERAL DESCRIPTION

Page 12

MC68HC05V7 Specification Rev. 1.0

is enabled, all the Port C pins will act as negative edge sensitive IRQ sources. See

SECTION 9 PARALLEL I/O for more details on the I/O ports.

1.5.13

AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7

When the A/D converter is disabled, PD0-PD7 and PE0-PE7 are general purpose input

pins. The A/D converter is disabled upon exiting from reset. When the A/D converter is

enabled, one of these pins is the analog input to the A/D converter. The A/D control register

contains control bits to direct which of the analog inputs are to be converted at any one

time. A digital read of this pin when the A/D converter is enabled results in a read of logical

zero from the selected analog pin. A digital read of the remaining pins gives their correct

(digital) values. A/D inputs AD8-AD15 (Port E) are not bonded out in the 56-pin package.

See SECTION 10 A/D CONVERTER for more details on the operation of the A/D

subsystem.

1.5.14

PWM

This pin provides an output for the pulse width modulation feature of the on-chip

programmable timer. See SECTION 13 PULSE WIDTH MODULATOR for more details on

the operation of the PWM subsystem.

1.5.15

PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO

These four I/O lines comprise Port F. The state of any pin is software programmable and

all Port F lines are configured as inputs during power-on or reset. See SECTION 9

PARALLEL I/O for more details on the I/O ports. When the SPI subsystem is enabled, PF0-

PF3 become the data, clock and select lines for the SPI. See SECTION 14 SERIAL

PERIPHERAL INTERFACE for more details on the operation of the SPI subsystem.

1.5.16

BUS, LOAD, REXT1, REXT2

These pins provide the I/O interface and external biasing functions for the MDLC

subsystem. See SECTION 15 MESSAGE DATA LINK CONTROLLER for more details on

the operation of the MDLC subsystem. The regulator control logic monitors the BUS pin and

latches a rising edge to re-enable the primary voltage regulator if this mask option is

enabled.

1.5.17

VIGN

The VIGN pin is used by the internal voltage regulator power moding circuitry to indicate that

the regulator should power up. Its state is reflected in the IGNS bit of the MISC register.

The input voltage levels on this pin are ratioed to the voltage on VBATT. See the electrical

specifications. A smaller secondary regulator remains alive to power the VIGN pin logic

when the primary voltage regulator is powered down, allowing the power moding logic to

recognize and latch a rising edge on this pin and re-enable the primary regulator (power-

up). See SECTION 7

POWER SUPPLY AND REGULATION for a more detailed

description.

The VIGN pin has no function when the option to disable the on-chip voltage regulator is

selected and should be tied low.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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