HC05V7GRSSLASHD datasheet(46/170 Pages) NXP

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SECTION 5: INTERRUPTS

Page 32

MC68HC05V7 Specification Rev. 1.0

5.2

RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a

similar manner, as shown in Figure 5-1. A low level input on the RESET pin or internally

generated RST signal causes the program to vector to its starting address which is

specified by the contents of memory locations $3FFE and $3FFF. The I-bit in the condition

code register is also set. The MCU is configured to a known state during this type of reset

as described in SECTION 6 RESETS.

5.3

SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed

regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the

SWI instruction executes after interrupts that were pending before the SWI was fetched, or

before interrupts generated after the SWI was fetched. The interrupt service routine

address is specified by the contents of memory locations $3FFC and $3FFD.

5.4

HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is

set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables

the hardware interrupts. There are two types of hardware interrupts which are explained in

the following sections.

5.5

EXTERNAL INTERRUPT (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ

function is shown in Figure 5-2.

NOTE:

The BIH and BIL instructions will only apply to the level on the IRQ pin

itself, and not to the output of the logic OR function with the Port A and

Port C IRQ interrupts. The state of the individual Port A and Port C pins

can be checked by reading the appropriate Port A and Port C pins as

inputs.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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