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HC05V7GRS/D Scheda tecnica(PDF) 36 Page - NXP Semiconductors

Il numero della parte HC05V7GRS/D
Spiegazioni elettronici  Low cost, HC05 Core
PDF  170 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC05V7GRS/D Scheda tecnica(HTML) 36 Page - NXP Semiconductors

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SECTION 3: EPROM and EEPROM
Page 22
MC68HC05V7 Specification Rev. 1.0
Table 3-1:
Erase Mode Select
3.1.3
LATCH
When set, LATCH configures the EEPROM address and data bus for programming. When
LATCH is set, writes to the EEPROM array cause the data bus and the address bus to be
latched. This bit is readable and writable, but reads from the array are inhibited if the
LATCH bit is set and a write to the EEPROM space has taken place. When clear, address
and data buses are configured for normal operation. Reset clears this bit.
3.1.4
EERC - EEPROM RC Oscillator Control
When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU
clock. After setting the EERC bit, delay a time t
RCON to allow the RC oscillator to stabilize.
This bit is readable and writable and should be set by the user when the internal bus
frequency falls below 1.5 MHz. Reset clears this bit.
3.1.5
EEPGM - EEPROM Programming Power Enable
EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM
turns on the charge pump and enables the programming (or erasing) power to the
EEPROM array. When clear, this power is switched off. This will enable pulsing of the
programming voltage to be controlled internally. This bit can be read at any time, but can
only be written to if LATCH=1. If LATCH is not set, then EEPGM cannot be set. Reset clears
this bit.
3.1.6
PROGRAMMING/ERASING PROCEDURES
To program a byte of EEPROM, set LATCH = CPEN = 1, set ER1 = ER0 = 0, write data to
the desired address, and then set EEPGM for a time t
EEPGM.
In general, all bits should be erased before being programmed. However, if write/erase
cycling is a concern, a procedure can be followed to minimize the cycling of each bit in each
EEPROM byte. The erased state is 1; therefore, if any bits within the byte need to be
changed from a 0 to a 1, the byte must be erased before programming. The decision
1
ER1
0
0
1
1
Bulk Erase
ER0
MODE
0
No Erase
1
Byte Erase
0
Block Erase
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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