HC05V7GRSSLASHD datasheet(4/170 Pages) NXP

4 / 170 page

Page iv

MC68HC05V7 Specification Rev. 1.0

SECTION 4

CPU CORE .....................................................................25

4.1

REGISTERS............................................................................. 25

4.1.1

ACCUMULATOR (A) .......................................................... 25

4.1.2

INDEX REGISTER (X) ........................................................ 25

4.1.3

STACK POINTER (SP) ....................................................... 26

4.1.4

PROGRAM COUNTER (PC) .............................................. 26

4.1.5

CONDITION CODE REGISTER (CCR) .............................. 26

SECTION 5

INTERRUPTS .................................................................29

5.1

CPU INTERRUPT PROCESSING ........................................... 29

5.2

RESET INTERRUPT SEQUENCE........................................... 32

5.3

SOFTWARE INTERRUPT (SWI) ............................................. 32

5.4

HARDWARE INTERRUPTS .................................................... 32

5.5

EXTERNAL INTERRUPT (IRQ) ............................................... 32

5.5.1

IRQ CONTROL/STATUS REGISTER (ICSR) $1F ............. 34

5.5.2

EXTERNAL INTERRUPT TIMING ...................................... 36

5.6

16-BIT TIMER INTERRUPT ..................................................... 37

5.7

MDLC INTERRUPT.................................................................. 37

5.8

SPI INTERRUPT ...................................................................... 37

5.9

8-BIT TIMER INTERRUPT ....................................................... 38

SECTION 6

RESETS..........................................................................39

6.1

EXTERNAL RESET (RESET) .................................................. 39

6.2

INTERNAL RESETS ................................................................ 40

6.2.1

POWER-ON RESET (POR)................................................ 40

6.2.2

OPERATION IN STOP AND WAIT ..................................... 40

6.2.3

COMPUTER OPERATING PROPERLY RESET (COPR) .. 42

6.2.4

LOW-VOLTAGE RESET (LVR) .......................................... 43

6.2.5

ILLEGAL ADDRESS ........................................................... 44

6.2.6

DISABLED STOP INSTRUCTION ...................................... 44

SECTION 7

POWER SUPPLY AND REGULATION ........................................ 45

7.1

INTERNAL POWER SUPPLY .................................................. 45

7.1.1

PRIMARY 5V REGULATOR ............................................... 45

7.1.2

SECONDARY REGULATOR .............................................. 45

7.2

MISCELLANEOUS REGISTER ............................................... 46

7.2.1

IGNS - Ignition status bit ..................................................... 46

7.2.2

OCE - Output compare enable ........................................... 46

7.2.3

PDC - Power Down Control ................................................ 46

7.3

POWER MODING .................................................................... 47

7.4

REGULATOR CONTROL LOGIC ............................................ 49

7.4.1

MASK OPTIONS................................................................. 50

7.5

POWER SUPPLY CONFIGURATION ..................................... 53

7.5.1

DECOUPLING RECOMMENDATIONS .............................. 53

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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