HC05V7GRSSLASHD datasheet(75/170 Pages) NXP

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SECTION 9: PARALLEL I/O

Page 61

MC68HC05V7 Specification Rev. 1.0

SECTION 9

PARALLEL I/O

In the Single-Chip Mode there are 28 bidirectional I/O lines arranged as three 8-bit I/O ports

(Ports A, B and C) and one 4-bit I/O port (Port F), and 16 input only lines arranged as two

8-bit ports (Ports D and E). The individual bits in the I/O ports are programmable as either

inputs or outputs under software control by the data direction registers (DDRs). The Port A

and Port C pins also have the additional properties of acting as additional IRQ interrupt

input sources.

9.1

PORT A AND PORT C

Port A and Port C are 8-bit bidirectional ports which share all of their pins with the IRQ

interrupt system as shown in Figure 9-1. Each pin is controlled by the corresponding bits in

a data direction register and a data register. The Port A Data Register is located at address

$0000.The Port C Data Register is located at address $0002. The Port A Data Direction

is located at address $0006. Reset clears DDRA and DDRC. The Data Registers are

unaffected by reset.

Figure 9-1:

Port A and Port C I/O Circuitry

9.1.1

PORT A/C DATA REGISTERS

Each Port A/C I/O pin has a corresponding bit in the Port A/C Data Register. When a Port

A/C pin is programmed as an output the state of the corresponding data register bit

determines the state of the output pin. When a Port A/C pin is programmed as an input, any

to IRQ interrupt system

Port A/C Bits 0 thru 7

Read $0000/02

Write $0000/02

Read $0004/06

Data

I/O

Output

Internal HC05

Data Bus

Reset

(RST)

Write $0004/06

Data Direction

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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