HC05V7GRSSLASHD datasheet(10/170 Pages) NXP

10 / 170 page

Page x

MC68HC05V7 Specification Rev. 1.0

Figure 9-1:

Port A and Port C I/O Circuitry ............................................................ 61

Figure 9-2:

Port B I/O Circuitry .............................................................................. 63

Figure 9-3:

Port D and Port E Circuitry .................................................................. 64

Figure 10-1:

A/D Status and Control Register ......................................................... 66

Figure 10-2:

A/D Data Register ............................................................................... 67

Figure 11-1:

16-Bit Timer Block Diagram ................................................................ 69

Figure 11-2:

Timer Control Register - $12 ............................................................... 72

Figure 11-3:

Timer Status Register - $13 ................................................................ 72

Figure 11-4:

TCAP Timing ....................................................................................... 74

Figure 12-1:

Core Timer Block Diagram .................................................................. 75

Figure 12-2:

Core Timer Control and Status Register ............................................. 76

Figure 12-3:

Timer Counter Register ....................................................................... 78

Figure 13-1:

PWM Block Diagram ........................................................................... 79

Figure 13-2:

PWM Waveform Examples (POL = 1)................................................. 80

Figure 13-3:

PWM Waveform Examples (POL = 0)................................................. 80

Figure 13-4:

PWM Write Sequences ....................................................................... 81

Figure 13-5:

PWM Control Register ........................................................................ 81

Figure 13-6:

PWM Data Register ............................................................................ 82

Figure 14-1:

Data Clock Timing Diagram ................................................................ 84

Figure 14-2:

Serial Peripheral Interface Block Diagram .......................................... 86

Figure 14-3:

Serial Peripheral Interface Master-Slave Interconnection ................... 87

Figure 14-4:

SPI Control Register (SPCR) .............................................................. 87

Figure 14-5:

Serial Peripheral Rate Selection ......................................................... 88

Figure 14-6:

SPI Status Register (SPSR)................................................................ 88

Figure 15-1:

MDLC Operating Modes State Diagram ............................................. 93

Figure 15-2:

MDLC User Registers ......................................................................... 95

Figure 15-3:

MDLC Control Register (MCR) ........................................................... 96

Figure 15-4:

MDLC Status Register (MSR) ............................................................. 99

Figure 15-5:

MDLC Tx Control Register (MTCR) .................................................. 100

Figure 15-6:

MDLC Rx Status Register (MRSR) ................................................... 101

Figure 15-7:

MDLC Rx/Tx Buffers Outline ............................................................. 105

Figure 15-8:

MDLC Protocol Handler Outline ........................................................ 108

Figure 15-9:

MDLC Rx Digital Filter Block Diagram .............................................. 112

Figure 15-10:

J1850 Bus Message Format (VPW).................................................. 114

Figure 15-11:

J1850 VPW Symbols ........................................................................ 116

Figure 15-12:

J1850 VPW Passive Symbols........................................................... 118

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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