HC05V7GRSSLASHD datasheet(56/170 Pages) NXP

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SECTION 6: RESETS

Page 42

MC68HC05V7 Specification Rev. 1.0

6.2.3

COMPUTER OPERATING PROPERLY RESET (COPR)

The MCU contains a watchdog timer that automatically times out if not reset (cleared) within

a specific time by a program reset sequence. If the COP watchdog timer is allowed to time-

out, an internal reset is generated to reset the MCU. Regardless of an internal or external

RESET, the MCU comes out of a COP reset according to the standard rules of mode

selection.

The COP reset function is enabled or disabled by a mask option and is verified during

production testing.

The COP Watchdog reset will activate the internal pulldown device connected to the

RESET pin.

6.2.3.1

RESETTING THE COP

Preventing a COP reset is done by writing a “0” to the COPF bit. This action will reset the

counter and begin the time-out period again. The COPF bit is bit 0 of address $3FF0. A

read of address $3FF0 will return user data programmed at that location.

6.2.3.2

COP DURING WAIT MODE

The COP will continue to operate normally during WAIT mode. The software should pull the

device out of WAIT mode periodically and reset the COP by writing to the COPF bit to

prevent a COP reset.

6.2.3.3

COP DURING STOP MODE

When the STOP enable mask option is selected, STOP mode disables the oscillator circuit

and thereby turns the clock off for the entire device. The COP counter will be reset when

STOP mode is entered. If a reset is used to exit STOP mode, the COP counter will be held

in reset during the 4064 cycles of start up delay. If any operable interrupt is used to exit

STOP mode, the COP counter will not be reset during the 4064 cycle start up delay and

will have that many cycles already counted when control is returned to the program.

6.2.3.4

COP WATCHDOG TIMER CONSIDERATIONS

The COP Watchdog Timer is active in all modes of operation if enabled by a mask option.

If the COP Watchdog Timer is selected by a mask option, any execution of the STOP

instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the

oscillator to halt and prevent the COP Watchdog Timer from timing out. Therefore, it is

recommended that the STOP instruction should be disabled if the COP Watchdog Timer

is enabled.

If the COP Watchdog Timer is selected by a mask option, the COP will reset the MCU when

it times out. Therefore, it is recommended that the COP Watchdog should be disabled for

a system that must have intentional uses of the WAIT Mode for periods longer than the

COP time-out period.

The recommended interactions and considerations for the COP Watchdog Timer, STOP

instruction, and WAIT instruction are summarized in Table 6-1.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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