HC05V7GRSSLASHD datasheet(92/170 Pages) NXP

92 / 170 page

SECTION 12: CORE TIMER

Page 78

MC68HC05V7 Specification Rev. 1.0

12.3

CORE TIMER COUNTER REGISTER (CTCR) $09

The Timer Counter Register is a read-only register which contains the current value of the

8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU

clock (E/4) and can be used for various functions including a software input capture.

Extended time periods can be attained using the TOF function to increment a temporary

RAM storage location thereby simulating a 16-bit (or more) counter.

Figure 12-3:

Timer Counter Register

The power-on cycle clears the entire counter chain and begins clocking the counter. After

4064 cycles, the power-on reset circuit is released which again clears the counter chain and

allows the device to come out of reset. At this point, if RESET is not asserted, the timer will

start counting up from zero and normal device operation will begin. When RESET is

asserted anytime during operation (other than POR), the counter chain will be cleared.

12.4

TIMER DURING WAIT MODE

The CPU clock halts during the WAIT mode, but the timer remains active. If interrupts are

enabled, a timer interrupt will cause the processor to exit the WAIT mode. The COP is

always enabled while in user mode.

$09

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Scheda tecnica(PDF) 92 Page - NXP Semiconductors